Abstract: A semiconductor circuit for a SRAM cell includes a first transistor and a second transistor on a substrate. The first transistor includes a first source contact over and coupled to a first source structure, a first drain contact over and coupled to a first drain structure, and a first gate structure laterally coupled between the first source contact and the first drain contact. The second transistor includes a second source contact over and coupled to a second source structure, a second drain contact over and coupled to a second drain structure, and a second gate structure laterally coupled between the second source contact and the second drain contact. The first drain contact is coupled to a bit line and has an air spacer on a sidewall thereof. The first source contact or the second source contact has no air spacer on a sidewall thereof.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a functional cell region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region including a first cutting feature and a first contact rail in the first cutting feature. The semiconductor structure also includes a first power rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell and including a second cutting feature and second contact rail in the second cutting feature. The semiconductor structure also includes an insulating strip extending from the first cutting feature to the second cutting feature in a first direction.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source/drain feature and a second source/drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source/drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source/drain feature.

Abstract: A semiconductor structure includes a memory cell, one or more logic cells configured to provide logic function to the memory cell, and an interconnect structure disposed over the memory cell and the one or more logic cells. The interconnect structure includes a bit line, a bit line bar, a first voltage line, and a second voltage line located in a same metal line layer of the interconnect structure. At least one of the bit line and the bit line bar extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell. At least one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell.

Abstract: An integrated circuit is provided and includes a first gate structure shared by a first transistor in a first semiconductor level and a second transistor in a second semiconductor level; a first conductive segment shared by a third transistor and a fourth transistor that are disposed in the first semiconductor level; a first connection structure coupling the first gate structure to the first conductive segment on a first side of the integrated circuit; a second gate structure shared by the fourth transistor and a fifth transistor that is disposed in a second semiconductor level; a second connection structure coupled to the second gate structure and disposed on a second side, different from the first side, of the integrated circuit; and a second connection segment corresponding to a first terminal of the second transistor and coupled to the second connection structure.

Abstract: A method includes providing a structure. The structure includes a substrate, a first stack of alternating first channel layers and first sacrificial layers over the substrate, a first source/drain trench exposing sidewalls of the first sacrificial layers, a second stack of alternating second channel layers and second sacrificial layers over the substrate, and a second source/drain trench exposing sidewalls of the second sacrificial layers. The method further includes performing a first etching process to selectively remove the first sacrificial layers and the second sacrificial layers, performing a second etching process to the first channel layers but not the second channel layers, forming a first source/drain feature in the first source/drain trench and a second source/drain feature in the second source/drain trench, and forming a first gate structure wrapping around the first channel layers and a second gate structure wrapping around the second channel layers.

Abstract: In an embodiment, a semiconductor device includes a plurality of first nanostructures, the plurality of first nanostructures extending between first source/drain regions, a plurality of second nanostructures over the plurality of first nanostructures, the plurality of second nanostructures extending between second source/drain regions, a first gate stack around the plurality of first nanostructures, a second gate stack over the first gate stack and disposed around the plurality of second nanostructures, where a first portion of the second gate stack is disposed above the plurality of second nanostructures, gate spacers on sidewalls of the first portion of the second gate stack, and a first metal contact that is in physical contact with a first source/drain region of the second source/drain regions, where an air-gap is disposed between a sidewall of the first metal contact and a sidewall of a first gate spacer of the gate spacers.

Abstract: An integrated circuit includes a first SRAM cell and a second SRAM cell, each including a plurality of field-effect transistors (FETs), a front metal line over the FETs and a back metal line below the FETs, and a middle strap area disposed between the first SRAM cell and the second SRAM cell. The middle strap area includes a plurality of gate stacks extending lengthwise along a direction, a gate isolation structure extending through a gate stack of the plurality of gate stacks, a feedthrough via (FTV) embedded in the gate isolation structure, a first dielectric gate disposed between the conductive structure and the first SRAM cell, and a second dielectric gate disposed between the conductive structure and the second SRAM cell. The FTV electrically couples the front metal line and the back metal line.

Abstract: A memory cell includes an active region extending lengthwise along a first direction and first and second gate structures extending lengthwise along a second direction different from the first direction. The first gate structure engages the active region in forming a first transistor, and the second gate structure engages the active region in forming a second transistor. The memory cell further includes a first epitaxial feature disposed on a source region of the first transistor, a second epitaxial feature disposed on a common drain region of the first and second transistors, a backside contact disposed under and in electrical coupling with the first epitaxial feature, a backside signal line disposed under and in electrical coupling with the backside contact, and a first frontside contact disposed above and in electrical coupling with the second epitaxial feature.

Abstract: A memory cell includes a first active region providing a plurality of first nano-structures for a write-port pass-gate transistor, a second active region providing a plurality of second nano-structures for a write-port pull-up transistor, and a third active region providing a plurality of third nano-structures for a read-port pull-down transistor. The first active region has a first width, the second active region has a second width, and the third active region having a third width. The third width is larger than the first width, and the first width is larger than the second width.

Abstract: A method of fabricating a semiconductor device includes forming a first active region and a second active region over a substrate, depositing an isolation structure between the first and second active regions, forming a gate structure across the first active region and the second active region, forming a trench dividing the gate structure into a first segment and a second segment, depositing a dielectric feature in the trench, thinning the substrate and the isolation structure to expose a bottom surface of the dielectric feature, selectively removing a surface layer of the dielectric feature to form an air gap, and depositing a seal layer capping the air gap.

Abstract: Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. In some embodiments, an implantation process is performed to implant a dopant into a S/D region to improve device performance. For example, source/drain regions of the transistors in a SRAM cell may be enhanced by additional dopants to improve the SRAM cell performance.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a first source/drain region, a second source/drain region disposed adjacent the first source/drain region, a contact etch stop layer disposed over the first source/drain region, a first interlayer dielectric (ILD) layer disposed over the contact etch stop layer, an etch stop layer disposed over a top surface of the contact etch stop layer and a top surface of the first ILD layer, a second ILD layer disposed over the etch stop layer, a first conductive feature disposed below the first and second source/drain regions, and a second conductive feature disposed above the first and second source/drain regions. The second conductive feature is electrically connected to the first and second source/drain regions, and the first and second conductive features are in contact with each other.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a first source/drain region, a second source/drain region disposed adjacent the first source/drain region, and a contact etch stop layer disposed over the first source/drain region. A top surface of the first source/drain region is covered by the contact etch stop layer. The structure further includes a first conductive feature disposed below the first and second source/drain regions, and the first conductive feature is electrically connected to the first and second source/drain regions.

Abstract: Semiconductor devices and methods are provided. An exemplary method includes receiving a transistor comprising a gate structure over a channel region, first and second source/drain features coupled to the channel region, and a dielectric structure over the first and the second source/drain features; forming a first trench extending through the dielectric structure to expose the first source/drain feature and a second trench extending through the dielectric structure to expose the second source/drain feature; forming a mask layer covering the first trench, wherein an opening of the mask layer exposes a portion of the second trench; after the forming of the mask layer, performing an ion implantation process to form a doped region in the second source/drain feature; and after the performing of the ion implantation process, forming a first source/drain contact in the first trench and a second source/drain contact in the second trench.

Abstract: A semiconductor structure according to the present disclosure includes a backside metal line and a backside contact structure that includes a bar portion disposed on the backside metal line, a first via extending from the bar portion, a second via extending from the bar portion, and a protrusion disposed between the first via and the second via. The semiconductor structure also includes a first source/drain feature over the first via, a second source/drain feature over the second via, and a gate isolation feature disposed between the first via and the second via. The protrusion extends into the gate isolation feature.

Abstract: A semiconductor structure includes an active region including a semiconductor fin base, a stack of nanostructures over the semiconductor fin base, and an epitaxial feature over the semiconductor fin base and connected to at least one of the nanostructures, the active region extending lengthwise in a first direction. The semiconductor structure further includes a gate structure wrapping around each of the nanostructures, the gate structure extending lengthwise in a second direction perpendicular to the first direction, and a backside butted contact disposed directly under and electrically connected to the epitaxial feature and the gate structure. A portion of the backside butted contact extends into the gate structure and the epitaxial feature.

Abstract: Semiconductor devices and methods of forming the same are provided. An exemplary method includes forming a fin over a substrate, a first portion of the fin comprising a plurality of first channel layers interleaved by a plurality of first sacrificial layers, and a second portion of the fin comprising a plurality of second channel layers interleaved by a plurality of second sacrificial layers, forming a trench extending through the fin, laterally recessing the plurality of first sacrificial layers and the plurality of second sacrificial layers at different etch rates, and replacing a remaining portion of the plurality of first sacrificial layers with a first gate structure and replacing a remaining portion of the plurality of second sacrificial layers with a second gate structure.

Abstract: A memory device includes a substrate having a first side and a second side opposite to each other; a first transistor, a second transistor, and a third transistor formed at a first level on the first side of the substrate, the first to third transistors each formed with a first conductivity; and a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed at a second level on the first side of the substrate, the fourth to seventh transistors each formed with a second conductivity, wherein the first level is vertically disposed with respect to the second level. The first to seventh transistors operatively form a Static Random Access Memory (SRAM) cell.

Abstract: A memory device includes a substrate having a first side and a second side; a first transistor, a second transistor, a third transistor, and a fourth transistor formed on the first side, the first to fourth transistors each formed with a p-type conductivity; a fifth transistor and a sixth transistor formed on the first side and over the first to fourth transistors, the fifth to sixth transistors each formed with an n-type conductivity; a first interconnect structure formed on the first side and over the fifth to sixth transistors, and coupled to the first transistor, wherein the first interconnect structure is configured as a portion of a first bit line; and a second interconnect structure formed on the second side, and also coupled to the first transistor, wherein the second interconnect structure is configured as another portion of the first bit line.