Abstract: A semiconductor device includes: a first memory array with a first side; a second memory array with a second side that faces the first side; and a well pickup region between the first memory array along the first side and the second memory array along the second side, the well pickup region having a first region and a second region each with an n-well tap cell and a middle region with a p-well tap cell between the first region and the second region, wherein a first edge region of the first region is placed along the first side of the first memory array region and a second edge region of the second region is placed along the second side of the second memory array region; wherein the p-well tap cell includes a contiguous OD region for providing reverse bias to P-N junctions in the first and second memory array regions.

Abstract: A modular riser card, an electronic device having a modular riser card, and a method of determining a type of modular riser card pin connection are disclosed. The modular riser card includes a circuit board and a removable connector assembly. The circuit board includes a first receptacle having a plurality of first pins. The removable connector assembly includes a connector body defining a second receptacle having a plurality of second pins, and an opening formed in the connector body adjacent to the second receptacle. The connector body is mounted on the circuit board such that the first receptacle protrudes through the opening and is aligned with the second receptacle. The first and second receptacles form a riser card connector that is configured to removably receive an expansion card of an electronic device.

Abstract: A semiconductor device according to the present disclosure includes a first memory cell and a second memory cell. The first memory cell includes a first active region for n-type transistors and a second active region for p-type transistors. The first active region has a first width. The second active region has a second width. The first width is larger than the second width. The second memory cell includes a third active region for n-type transistors and a fourth active region for p-type transistors. The third active region has a third width. The fourth active region has a fourth width. The third width is larger than the fourth width. The first width is larger than the third width.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure includes forming a stack of channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shape structure, forming a dummy gate stack over a channel region of the fin-shape structure, recessing a source/drain region to form a source/drain trench, forming an epitaxial feature in the source/drain trench, after the forming of the epitaxial feature removing the dummy gate stack, releasing the channel layers in the channel region as channel members, forming a gate structure wrapping around each of the channel members, and after the forming of the gate structure performing an ion implantation to increase a dopant concentration of a dopant in the epitaxial feature.

Abstract: A semiconductor structure includes an active region including a stack of channel layers, a metal gate structure disposed over the stack of channel layers, a source/drain feature disposed over a source/drain region of the active region and adjacent to the stack of channel layers, and a backside via penetrating from a back side of the active region and extending to contact a channel layer of the stack of channel layers. The backside via is electrically connected to the source/drain feature through the channel layer of the stack of channel layers and contacts the metal gate structure.

Abstract: A semiconductor structure includes an epitaxial feature disposed in an active region, a frontside contact disposed directly above and in electrical coupling with the epitaxial feature, a metal gate stack, an inner spacer interposing the metal gate stack and the epitaxial feature, and a backside contact in physical contact with a bottom portion of the metal gate stack and in physical contact with a bottom portion of the frontside contact.

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

Abstract: A semiconductor device according to the present disclosure includes a logic cell and a memory array including a plurality of memory cells. The memory cells and the logic cell are arranged in a row, and a first plurality of the memory cells are positioned closer to the logic cell than a second plurality of the memory cells. A frontside interconnect structure is disposed over the memory cells and includes a frontside bit line. The frontside bit line is coupled to each of the memory cells arranged in the row. A backside interconnect structure is disposed under the memory cells and includes a backside bit line. The backside bit line is coupled to at least the first plurality of the memory cells. The frontside bit line is coupled to the backside bit line through a source/drain feature of a pass-gate transistor of one of the first plurality of the memory cells.

Abstract: A device includes a substrate, a contact, a first gate, a second gate, a dielectric feature between the gates, a via, and a conductive line. The gates are each adjacent the contact and aligned lengthwise with each other along a first direction. A first sidewall of the dielectric feature defines an end-wall of the first gate. A second sidewall of the dielectric feature defines an end-wall of the second gate. The conductive line extends along a second direction. A projection of the conductive line onto a top surface of the dielectric feature passes between the first and second sidewalls. The via interfaces with the contact along a second plane. The via has a first dimension on the second plane along the second direction; the contact has a second dimension on the second plane along the second direction. The first dimension is greater than the second dimension.

Abstract: Semiconductor structures and methods for fabricating semiconductor structures are provided. A semiconductor structure includes a first fin extending in an X-direction and a second fin parallel to the first fin and distanced from the first fin in a Y-direction perpendicular to the X-direction. Each fin is formed with a first device area and a second device area aligned in the X-direction; an isolation region disposed between the fins; an isolation structure disposed between the device areas in each fin; and an isolation layer disposed under the fins. The isolation region contacts the isolation layer, the isolation structure contacts the isolation layer, and the isolation region contacts the isolation structure to isolate the first fin from the second fin and to isolate the first device area from the second device area in each fin.

Abstract: A riser cage assembly having a riser cage bracket and a fastener assembly coupled to the riser cage bracket is disclosed. The fastener assembly includes an enclosure, an actuator including drivers, a shaft, and a biasing member. The enclosure has a bore, guide teeth within the bore, and bays defined between the guide teeth. The actuator is movably coupled to an end of the enclosure with the drivers disposed within the bore. The shaft has blades disposed within the bore, and a locking arm protruding beyond the bore from another end of the enclosure. The actuator generates biasing force urging the shaft towards the end of the enclosure. The shaft is translatable along and rotatable along a vertical axis relative to the enclosure, by the actuator and the biasing member to removably fasten the riser cage bracket to the electronic device.

Abstract: One aspect of the present disclosure pertains to a device. The device includes a memory macro having a frontside and a backside along a vertical direction. The memory macro includes edge strap areas extending lengthwise along a first direction at edges of the memory macro, a memory cell area having a plurality of memory cells, where the memory cell area is disposed between the edge strap areas along a second direction perpendicular to the first direction, and a middle strap area extending lengthwise along the first direction and disposed between the edge strap areas along the second direction, where the middle strap area divides the memory cell area into two memory cell domains. The middle strap area includes a feedthrough circuit that routes a power signal line of one of the plurality of memory cells to the backside of the memory macro.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first active region in which first semiconductor layers and second semiconductor layers are alternatingly stacked over a first lower fin element. In a plan view, the active region includes a first portion and a second portion narrower than the first portion. The method also includes removing the first semiconductor layers of the first active region. The second semiconductor layers of the first portion of the first active region form first nanostructures, and the second semiconductor layers of the second portion of the first active region form second nanostructures. The method also includes forming a first gate stack to surround the first nanostructures, and forming a second gate stack to surround the second nanostructures.

Abstract: A semiconductor structure according to the present disclosure includes a first memory cell that includes a first pull-down transistor and a first pull-up transistor sharing a first gate structure extending along a first direction, a second pull-down transistor and a second pull-up transistor sharing a second gate structure extending along the first direction, a first pass-gate transistor having a third gate structure spaced apart but aligned with the second gate structure along the first direction, and a second pass-gate transistor having a fourth gate structure spaced apart but aligned with the first gate structure along the first direction, a frontside interconnect structure disposed over the first memory device, a backside interconnect structure disposed below the first memory device. A source of the second pull-down transistor is electrically coupled to the backside interconnect structure by way of a first backside contact via.

Abstract: A semiconductor structure according to the present disclosure includes a first memory array in a first cache and a second memory array in a second cache. The first memory array includes a plurality of first memory cells arranged in M1 rows and N1 columns. The second memory array includes a plurality of second memory cells arranged in M2 rows and N2 columns. The semiconductor structure also includes a first bit line coupled to a number of N1 first memory cells in one of the M1 rows, and a second bit line coupled to a number of N2 second memory cells in one of the M2 rows. N1 is smaller than N2, and a width of the first bit line is smaller than a width of the second bit line.

Abstract: A semiconductor device according to the present disclosure includes a memory array having a plurality of memory cells arranged in a row, and an interconnect structure disposed over the memory cells and having a bit line coupled to each of the memory cells arranged in the row. The bit line has a first segment coupled to a first portion of the memory cells and a second segment coupled to a second portion of the memory cells. The first segment has a first width and the second segment has a second width that is smaller than the first width.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a gate structure. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line are positioned at a first interconnect layer disposed over the gate structure and a read word line positioned at a second interconnect layer and electrically coupled to the gate structure, the second interconnect layer is disposed under the gate structure.

Abstract: An integrated circuit includes a first SRAM cell and a second SRAM cell, each including a plurality of field-effect transistors (FETs), a front metal line over the FETs and a back metal line below the FETs, and a middle strap area disposed between the first SRAM cell and the second SRAM cell. The middle strap area includes a plurality of gate stacks extending lengthwise along a direction, a gate isolation structure extending through a gate stack of the plurality of gate stacks, a feedthrough via (FTV) embedded in the gate isolation structure, a first dielectric gate disposed between the conductive structure and the first SRAM cell, and a second dielectric gate disposed between the conductive structure and the second SRAM cell. The FTV electrically couples the front metal line and the back metal line.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source/drain feature and a second source/drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source/drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source/drain feature.

Abstract: A semiconductor structure includes a first source/drain (S/D) epitaxial feature, a second S/D epitaxial feature adjacent to the first S/D epitaxial feature, an insulating structure between the first and the second S/D epitaxial features, and a shared S/D contact over top surfaces of the first and the second S/D epitaxial features. A center portion of the shared S/D contact is directly between a side surface of the first S/D epitaxial feature and a side surface of the second S/D epitaxial feature. The center portion is directly above the insulating structure. The semiconductor structure further includes a backside via penetrating through the insulating structure to directly land on a bottom surface of the center portion.