Patents by Inventor Jui-Lin Chen

Jui-Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384618
    Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 1, 2022
    Inventors: Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen, Chih-Hsuan Chen
  • Patent number: 11513281
    Abstract: A light source structure, a backlight module and a display are provided. The light source structure includes a substrate and plural light source groups. The light source groups are arranged on the substrate, in which each of the light source groups includes plural light-emitting units, and there is a first distance between any two adjacent light-emitting units in each of the light source groups, and there is a second distance between two closest light-emitting units that are respectively in any two adjacent light source groups. The second distance is smaller than the first distance.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: November 29, 2022
    Assignees: Radiant Opto-Electronics (Suzhou) Co., Ltd., Radiant Opto-Electronics Corporation
    Inventors: Jui-Lin Chen, Pin-Hsun Lee, Yen-Ping Cheng, Yuan-Jhang Chen, Ruei-Lin Huang
  • Publication number: 20220352180
    Abstract: A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (Vt) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.
    Type: Application
    Filed: September 1, 2021
    Publication date: November 3, 2022
    Inventors: Shih-Hao Lin, Chih-Hsiang Huang, Shang-Rong Li, Chih-Chuan Yang, Jui-Lin Chen, Ming-Shuan Li
  • Publication number: 20220352256
    Abstract: Semiconductor structures and methods of the forming the same are provided. A semiconductor structure according to the present disclosure includes a source feature and a drain feature, an active region between the source feature and the drain feature, a gate structure over the active region, a frontside interconnect structure disposed over the source feature, the drain feature, and the gate structure, a backside interconnect structure disposed below the source feature, the drain feature, and the gate structure, and a storage element disposed in the backside interconnect structure.
    Type: Application
    Filed: August 16, 2021
    Publication date: November 3, 2022
    Inventors: Hsin-Wen Su, Jui-Lin Chen, Shih-Hao Lin, Ming-Yen Chuang, Chenchen Jacob Wang, Lien-Jung Hung, Ping-Wei Wang
  • Patent number: 11482610
    Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO.
    Inventors: Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen, Chih-Hsuan Chen
  • Publication number: 20220328561
    Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.
    Type: Application
    Filed: August 20, 2021
    Publication date: October 13, 2022
    Inventors: Jui-Lin CHEN, Chenchen Jacob WANG, Hsin-Wen SU, Ping-Wei WANG, Yuan-Hao CHANG, Po-Sheng LU, Shih-Hao LIN
  • Publication number: 20220328498
    Abstract: Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ping-Wei Wang, Jui-Lin Chen, Yu-Kuan Lin
  • Publication number: 20220301646
    Abstract: The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Hsin-Wen Su, Shih-Hao Lin, Jui-Lin Chen, Lien-Jung Hung, Ping-Wei Wang
  • Patent number: 11412714
    Abstract: A pet monitoring method and a pet monitoring system according to embodiments of the disclosure are provided. The method is described hereinafter. An image is obtained by a photographic device. At least one of an exercise status detection, an excretion status detection and a danger status detection of a pet is performed according to the image. Pet management information is presented on a management interface of a remote device according to a detection result.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 16, 2022
    Assignee: Acer Incorporated
    Inventor: Jui-Lin Chen
  • Patent number: 11404424
    Abstract: Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ping-Wei Wang, Jui-Lin Chen, Yu-Kuan Lin
  • Publication number: 20220208037
    Abstract: The disclosure provides a display driving device and an operation method thereof. The display driving device includes a timing controller circuit and a driving circuit. The timing controller circuit performs oblique filter processing on an original image frame by an oblique filter with an oblique filter mask matrix to generate a processed image frame. The oblique filter comprises an oblique high-pass filter or a smoothing filter. Original pixel data of a current pixel in the original image frame is replaced with new pixel data when the oblique filter mask matrix is configured for the current pixel. The driving circuit drives a display panel module according to the processed image frame. The display panel module includes a tilt lenticular lens layer having a first tilt angle. A second tilt angle of the oblique filter mask matrix of the oblique filter processing corresponds to the first tilt angle.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 30, 2022
    Applicant: Acer Incorporated
    Inventors: Jui-Lin Chen, Chao-Shih Huang
  • Patent number: 11367494
    Abstract: The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen Su, Shih-Hao Lin, Jui-Lin Chen, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20220181332
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Publication number: 20220136675
    Abstract: A light source structure, a backlight module and a display device are described, in which the light source structure includes a substrate, plural partition walls, plural light-emitting units and plural package structures. The plural partition walls are disposed on the substrate so as to form plural accommodating spaces. The light-emitting units are disposed on the substrate and are located in the accommodating spaces. The package structures are filled in the accommodating spaces and cover the light-emitting units. A height of each package structure is smaller or equal to a height of each partition wall, and the height of each of the package structures which is located near a side portion of the substrate is smaller than the heights of the partition walls which are located near a center portion of the substrate.
    Type: Application
    Filed: January 17, 2022
    Publication date: May 5, 2022
    Inventors: Jui-Lin CHEN, Pin-Hsun LEE, Yuan-Jhang CHEN
  • Patent number: 11308830
    Abstract: The disclosure provides a display driving device and an operation method thereof. The display driving device includes a timing controller circuit and a driving circuit. The timing controller circuit performs oblique filter processing on an original image frame to generate a processed image frame. The driving circuit is coupled to the timing controller circuit to receive the processed image frame. The driving circuit drives a display panel module according to the processed image frame. The display panel module includes a tilt lenticular lens layer having a first tilt angle. A second tilt angle of a filter mask of the oblique filter processing corresponds to the first tilt angle.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: April 19, 2022
    Assignee: Acer Incorporated
    Inventors: Jui-Lin Chen, Chao-Shih Huang
  • Publication number: 20220113465
    Abstract: A light source structure, a backlight module and a display are provided. The light source structure includes a substrate and plural light source groups. The light source groups are arranged on the substrate, in which each of the light source groups includes plural light-emitting units, and there is a first distance between any two adjacent light-emitting units in each of the light source groups, and there is a second distance between two closest light-emitting units that are respectively in any two adjacent light source groups. The second distance is smaller than the first distance.
    Type: Application
    Filed: December 21, 2021
    Publication date: April 14, 2022
    Inventors: Jui-Lin CHEN, Pin-Hsun LEE, Yen-Ping CHENG, Yuan-Jhang CHEN, Ruei-Lin HUANG
  • Publication number: 20220088604
    Abstract: A microfluidic device and a microfluidic chip are provided. The microfluidic device includes the microfluidic chip, a pouring element, a flow adjustment element and a processor. The microfluidic chip includes a sorting assembly, a sample outlet channel, a pouring channel, a collection channel and a waste channel. The sorting assembly includes a sample inlet channel and a sorting chamber. The pouring element is connected to the pouring channel. The flow adjustment element is connected to a distal end of the sample outlet channel. The processor is configured to control the pouring element to pour a guiding fluid into the pouring channel entering the sample outlet channel and control the flow adjustment element to adjust a flow resistance of a drain section of the sample outlet channel.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 24, 2022
    Applicant: MiCareo Taiwan Co., Ltd.
    Inventors: Hui-Min Yu, Wei-Feng Fang, Ching-Chih Chang, Jui-Lin Chen
  • Publication number: 20220068413
    Abstract: The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Inventors: Hsin-Wen Su, Shih-Hao Lin, Jui-Lin Chen, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11264393
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Patent number: 11243344
    Abstract: A light source structure, a backlight module and a display are provided. The light source structure includes a substrate and plural light source groups. The light source groups are arranged on the substrate, in which each of the light source groups includes plural light-emitting units, and there is a first distance between any two adjacent light-emitting units in each of the light source groups, and there is a second distance between two closest light-emitting units that are respectively in any two adjacent light source groups. The second distance is smaller than the first distance.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: February 8, 2022
    Assignees: Radiant Opto-Electronics (Suzhou) Co., Ltd., Radiant Opto-Electronics Corporation
    Inventors: Jui-Lin Chen, Pin-Hsun Lee, Yen-Ping Cheng, Yuan-Jhang Chen, Ruei-Lin Huang