Abstract: Examples herein relate to printed circuit assemblies (PCA's). In one example, a PCA comprises a printed circuit board (PCB) having an elongated cut-out, the cut-out defining a first and a second opposite elongated edges on the PCB, a movable bracket having a standoff established on a surface of the movable bracket, the movable bracket connecting to the first and the second opposite elongated edges and a platform connector established on the PCB.

Abstract: A seat back recliner is revealed. A seat back is pivotally connected to and positioned on a rear end of a seat part of a chair while a cylinder is disposed between the seat part and the seat back. A reclined angle of the seat back is adjustable under control of the cylinder. Thereby a user sitting on the chair can directly adjust the seat back to the reclined angle required. The reclined seat back allows a user to lie back and have the greatest level of comfort and relaxation while sitting on the chair.

Abstract: A layout of a memory device is stored on a non-transitory computer-readable medium. The layout includes a plurality of active area regions, a lowermost interconnect layer, a plurality of memory cells, and a word line. The lowermost interconnect layer includes a first conductive layer over the plurality of active area regions, and a second conductive layer over the first conductive layer. The plurality of memory cells includes the plurality of active area regions. The word line is in the second conductive layer, and is coupled to the plurality of memory cells.

Abstract: A backlight module includes a light source, a light guide plate and a light-adjusting member. A light source chromaticity is measured from light generated by the light source. The light guide plate has a light-incident surface and a light-emitting surface. Light generated by the light source enters the light guide plate and emits out from the light-emitting surface. With the light-adjusting member, a first light guide plate chromaticity is measured from the light-emitting surface. There is a first difference value between the first light guide plate chromaticity and the light source chromaticity. Without the light-adjusting member, a second light guide plate chromaticity is measured from the light-emitting surface. There is a second difference value between the second light guide plate chromaticity and the light source chromaticity. The first difference value is different from the second difference value.

Abstract: A light guide assembly, a backlight module and a liquid crystal display (LCD) are provided. The backlight module includes a back plate, light guide plate, an adhesive member and a light source. The light guide plate is disposed on the back plate and includes a first optical surface, a second optical surface and a light-incident surface. The first optical surface is opposite to the second optical surface. The light-incident surface connects the first optical surface and the second optical surface. The first optical surface or the second optical surface of the light guide plate is set with a recess. The adhesive member is disposed in the recess to adhere the light guide plate to the back plate. The light source is disposed on the back plate and emits light toward the light guide plate.

Abstract: A light guide assembly, a backlight module and a liquid crystal display (LCD) are provided. The backlight module includes a back plate, light guide plate, an adhesive member and a light source. The light guide plate is disposed on the back plate and includes a first optical surface, a second optical surface and a light-incident surface. The first optical surface is opposite to the second optical surface. The light-incident surface connects the first optical surface and the second optical surface. The first optical surface or the second optical surface of the light guide plate is set with a recess. The adhesive member is disposed in the recess to adhere the light guide plate to the back plate. The light source is disposed on the back plate and emits light toward the light guide plate.

Abstract: A seat back recliner is revealed. A seat back is pivotally connected to and positioned on a rear end of a seat part of a chair while a cylinder is disposed between the seat part and the seat back. A reclined angle of the seat back is adjustable under control of the cylinder. Thereby a user sitting on the chair can directly adjust the seat back to the reclined angle required. The reclined seat back allows a user to lie back and have the greatest level of comfort and relaxation while sitting on the chair.

Abstract: A layout of a memory device is stored on a non-transitory computer-readable medium. The layout includes a plurality of active area regions, a lowermost interconnect layer, a plurality of memory cells, and a word line. The lowermost interconnect layer includes a first conductive layer over the plurality of active area regions, and a second conductive layer over the first conductive layer. The plurality of memory cells includes the plurality of active area regions. The word line is in the second conductive layer, and is coupled to the plurality of memory cells.

Abstract: A circuit comprises a first voltage line, a second voltage line parallel to the first voltage line, and a bit line between the first voltage line and the second voltage line. The bit line is separated from the first voltage line by a minimum distance allowed by a design rule. The bit line is closer to the first voltage line than to the second voltage line. A first capacitance value between the bit line and the first voltage line is different than a second capacitance value between the bit line and the second voltage line.

Abstract: A circuit comprises a first voltage line, a second voltage line parallel to the first voltage line, and a bit line between the first voltage line and the second voltage line. The bit line is separated from the first voltage line by a minimum distance allowed by a design rule. The bit line is closer to the first voltage line than to the second voltage line. A first capacitance value between the bit line and the first voltage line is different than a second capacitance value between the bit line and the second voltage line.

Abstract: A light guide assembly, a backlight module and a liquid crystal display (LCD) are provided. The backlight module includes a back plate, light guide plate, an adhesive member and a light source. The light guide plate is disposed on the back plate and includes a first optical surface, a second optical surface and a light-incident surface. The first optical surface is opposite to the second optical surface. The light-incident surface connects the first optical surface and the second optical surface. The first optical surface or the second optical surface of the light guide plate is set with a recess. The adhesive member is disposed in the recess to adhere the light guide plate to the back plate. The light source is disposed on the back plate and emits light toward the light guide plate.

Abstract: A light guide assembly, a backlight module and a liquid crystal display (LCD) are provided. The backlight module includes a back plate light guide plate, an adhesive member and a light source. The light guide plate is disposed on the back plate and includes a first optical surface, a second optical surface and a light-incident surface. The first optical surface is opposite to the second optical surface. The light-incident surface connects the first optical surface and the second optical surface. The first optical surface or the second optical surface of the light guide plate is set with recess. The adhesive member is disposed in the recess to adhere the light guide plate to the back plate. The light source is disposed on the back plate and emits light toward the light guide plate.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: A light guide assembly, a backlight module and a liquid crystal display (LCD) are provided. The backlight module includes a back plate light guide plate, an adhesive member and a light source. The light guide plate is disposed on the back plate and includes a first optical surface, a second optical surface and a light-incident surface. The first optical surface is opposite to the second optical surface. The light-incident surface connects the first optical surface and the second optical surface The first optical surface or the second optical surface of the light guide plate is set with recess. The adhesive member is disposed in the recess to adhere the light guide plate to the back plate. The light source is disposed on the back plate and emits light toward the light guide plate.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.