Abstract: A method of forming a semiconductor device includes providing a structure that includes a substrate, a first fin and a second fin, a first gate structure engaging the first fin, and a second gate structure engaging the second fin; depositing a dielectric layer over the first and second gate structures; etching the dielectric layer, thereby forming a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein the first gate contact opening has a first length that is larger than a second length of the second gate contact opening; and filling the first and second gate contact openings with conductive material, thereby forming a first gate contact engaging the first gate structure and a second gate contact engaging the second gate structure.

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.

Abstract: Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.

Abstract: A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction.

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

Abstract: A light-emitting mechanism comprises at least one LED, an optical unit disposed on the LED, and at least one dimming unit disposed on the optical unit and corresponding to the LED. The dimming unit includes a shading component disposed directly above the corresponding LED, the size of the shading component is greater than or equal to the size of the LED below the shading component, and the adjacent shading components are not contact with each other. The invention also provides a backlight module including the light-emitting mechanism.

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

Abstract: A light source structure, a backlight module and a display are provided. The light source structure includes a substrate and plural light source groups. The light source groups are arranged on the substrate, in which each of the light source groups includes plural light-emitting units, and there is a first distance between any two adjacent light-emitting units in each of the light source groups, and there is a second distance between two closest light-emitting units that are respectively in any two adjacent light source groups. The second distance is smaller than the first distance.

Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.

Abstract: A light source structure, a backlight module and a display are provided. The light source structure includes a substrate and plural light source groups. The light source groups are arranged on the substrate, in which each of the light source groups includes plural light-emitting units, and there is a first distance between any two adjacent light-emitting units in each of the light source groups, and there is a second distance between two closest light-emitting units that are respectively in any two adjacent light source groups. The second distance is smaller than the first distance.

Abstract: A light-adjusting film is mounted between a color conversion layer and a display panel of a direct type backlight module and has a substrate and at least one light-adjusting layer. The substrate has a central area and a surrounding area. The at least one light-adjusting layer has a pigment and is mounted on the substrate. A content of the pigment is gradually decreased from the surrounding area to the central area. The color of the pigment of the light-adjusting film is a correction color of lights emitted from light emitting surface of the color conversion layer in the backlight module.

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

Abstract: A method of forming a semiconductor device includes providing a structure that includes a substrate, a first fin and a second fin, a first gate structure engaging the first fin, and a second gate structure engaging the second fin; depositing a dielectric layer over the first and second gate structures; etching the dielectric layer, thereby forming a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein the first gate contact opening has a first length that is larger than a second length of the second gate contact opening; and filling the first and second gate contact openings with conductive material, thereby forming a first gate contact engaging the first gate structure and a second gate contact engaging the second gate structure.

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

Abstract: A light source structure, a backlight module and a display are provided. The light source structure includes a substrate and plural light source groups. The light source groups are arranged on the substrate, in which each of the light source groups includes plural light-emitting units, and there is a first distance between any two adjacent light-emitting units in each of the light source groups, and there is a second distance between two closest light-emitting units that are respectively in any two adjacent light source groups. The second distance is smaller than the first distance.

Abstract: A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction.

Abstract: In accordance with some embodiments, a fluid sample collection and retrieval apparatus including a microfluidic chip, a retrieval tube, a first switch, a second switch and a processor is provided. The microfluidic chip includes a first sample channel, a first fluid directing channel assembly, a first confluence chamber, a first collection channel, a first waste channel, and a retrieval hole. The retrieval hole passes through an outer surface of the microfluidic chip. The retrieval tube is connected to the retrieval hole. The first switch is connected to the microfluidic chip. The second switch is attached to the retrieval tube. The processor is configured to activate the first switch to operate the flow adjustment of the first fluid directing channel assembly and activate the second switch to operate a sample collection in the first collection channel within duration of operating the flow adjustment of the first fluid directing channel assembly.

Abstract: A light-adjusting film is mounted between a color conversion layer and a display panel of a direct type backlight module and has a substrate and at least one light-adjusting layer. The substrate has a central area and a surrounding area. The at least one light-adjusting layer has a pigment and is mounted on the substrate. A content of the pigment is gradually decreased from the surrounding area to the central area. The color of the pigment of the light-adjusting film is a correction color of lights emitted from light emitting surface of the color conversion layer in the backlight module.

Abstract: The present subject matter relates to screws for tool-less assembling of an electronic board on a chassis. In an example implementation, the screw comprises a threaded pin to secure the screw on the electronic board using a nut. The screw also comprises a screw head that fits into a hook on the chassis when the electronic board is assembled on the chassis. The screw further comprises a flange integral to the screw and positioned between the threaded pin and the screw head. The flange is extended radially to support the electronic board and is positioned at a distance from the screw head based on a gap to be maintained between the electronic board and the chassis.