Patents by Inventor Jui-Pin Hung

Jui-Pin Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Packaging methods and packaged semiconductor devices
    Patent number: 10128175
    Abstract: Packaging methods and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes forming first contact pads on a carrier, forming a wiring structure over the first contact pads, and forming second contact pads over the wiring structure. A first packaged semiconductor device is coupled to a first set of the second contact pads, and a second packaged semiconductor device is coupled to a second set of the second contact pads. The carrier is removed. The second packaged semiconductor device comprises a different package type than the first packaged semiconductor device.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jing-Cheng Lin, Jui-Pin Hung
  • SEMICONDUCTOR PACKAGE STRUCTURE
    Publication number: 20180294237
    Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer and an interconnecting structure. The first redistribution layer has a first surface and a second surface opposite to each other. The second redistribution layer is disposed over the first surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the first surface. The interconnecting structure is disposed between and electrically connected to the first redistribution layer and the second redistribution layer, wherein the interconnecting structure comprises a conductive post and a conductive bump stacked to each other.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: JUI-PIN HUNG, FENG-CHENG HSU, SHUO-MAO CHEN, SHIN-PUU JENG, DE-DUI MARVIN LIAO
  • Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer
    Publication number: 20180286839
    Abstract: A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the butter layer, wherein the guiding trench is misaligned with the device die.
    Type: Application
    Filed: June 7, 2018
    Publication date: October 4, 2018
    Inventors: Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Integrated fan-out structure with guiding trenches in buffer layer
    Patent number: 10083946
    Abstract: A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • SEMICONDUCTOR PACKAGE DEVICE
    Publication number: 20180269124
    Abstract: A semiconductor device includes a die having a pad, a passivation disposed aver the die and a portion of the pad, a polymer disposed over the passivation, a molding surrounding the die and the polymer, and an interface between the polymer and the molding. The interface and the passivation define an angle less than or greater than approximately 90°.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: NAI-WEI LIU, JUI-PIN HUNG, JING-CHENG LIN
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180269189
    Abstract: A method of manufacturing a structure includes: providing a substrate; forming an adhesive layer over the substrate; forming an interconnect layer comprising a metal line and a metal via over the adhesive layer; forming a plurality of conductive pads over the interconnect layer; forming conductive pillars over the interconnect layer; disposing a first semiconductor die over the conductive pads, the first semiconductor die being spaced apart from the conductive pillars; bonding a second semiconductor die with the conductive pillars; and removing the substrate and the adhesive layer to expose a conductive portion of the interconnect layer.
    Type: Application
    Filed: May 23, 2018
    Publication date: September 20, 2018
    Inventors: SHIN-PUU JENG, JUI-PIN HUNG, FENG-CHENG HSU
  • Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
    Patent number: 10079225
    Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs. The openings surrounding the end-portions of the TPVs of the die package enable solders of the bonding structures formed between another die package to remain in the openings without sliding and consequently increases yield and reliability of the bonding structures. Polymers may also be added to fill the openings surrounding the TPVs or even the space between the die packages to reduce cracking of the bonding structures under stress.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Li-Hui Cheng
  • Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
    Patent number: 10079159
    Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs. The openings surrounding the end-portions of the TPVs of the die package enable solders of the bonding structures formed between another die package to remain in the openings without sliding and consequently increases yield and reliability of the bonding structures. Polymers may also be added to fill the openings surrounding the TPVs or even the space between the die packages to reduce cracking of the bonding structures under stress.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Li-Hui Cheng
  • Structure and formation method for chip package
    Patent number: 10074637
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng
  • SEMICONDUCTOR PACKAGE
    Publication number: 20180247900
    Abstract: Some embodiments relate to a semiconductor package. The semiconductor package includes a redistribution layer (RDL) including a first metal layer and a second metal layer. The second metal layer is stacked over the first metal layer and is coupled to the first metal layer through a via. A first semiconductor die is disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL, and the RDL enables fan-out connection of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die and over the RDL. The second semiconductor die is bonded to the RDL by a plurality of conductive bump structures.
    Type: Application
    Filed: April 30, 2018
    Publication date: August 30, 2018
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • Integrated fan-out package structures with recesses in molding compound
    Patent number: 10062662
    Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
    Patent number: 10049989
    Abstract: A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin
  • Method of manufacturing a semiconductor device including through silicon plugs
    Patent number: 10049931
    Abstract: A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semicondutor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Jui-Pin Hung, Chien Ling Hwang
  • Semiconductor package and manufacturing method of the same
    Patent number: 10050024
    Abstract: The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged die having a carrier surface and a molding surface, and a first die structure in proximity to the carrier surface. An active region of the first die structure is electrically coupled to the packaged die through a solder. The second layer includes a second die structure, the second die structure being connected to the active region of the first die structure by a first redistributed layer (RDL). The conductive array is connected to an active region of the second die structure by a second RDL. The present disclosure also provides a method for manufacturing the aforesaid semiconductor package.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jui-Pin Hung, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
  • Three-Layer Package-on-Package Structure and Method Forming Same
    Publication number: 20180226378
    Abstract: A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of redistribution lines, and bonding a first device die to the first plurality of redistribution lines. The first metal post and the first device die are encapsulated in a first encapsulating material. The first encapsulating material is then planarized. The method further includes forming a second metal post over and electrically connected to the first metal post, attaching a second device die to the first encapsulating material through an adhesive film, encapsulating the second metal post and the second device die in a second encapsulating material, planarizing the second encapsulating material, and forming a second plurality of redistributions over and electrically coupling to the second metal post and the second device die.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Jui-Pin Hung, Feng-Cheng Hsu, Shin-Puu Jeng
  • Interconnect Structure for Package-on-Package Devices and a Method of Fabricating
    Publication number: 20180211901
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10032725
    Abstract: A semiconductor structure includes a plurality of devices, each of the plurality of devices includes a first surface disposed with an active component; and a molding disposed between the plurality of devices and including a first surface, wherein one of the plurality of devices has substantially different height from another one of the plurality of devices, and the first surface of the molding includes a recessed portion recessed from one of the first surfaces of the plurality of devices.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Jui-Pin Hung
  • Integrated Passive Device Package and Methods of Forming Same
    Publication number: 20180197755
    Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Jui-Pin Hung, Shin-Puu Jeng
  • Wafer-level packaging mechanisms
    Patent number: 10008463
    Abstract: A semiconductor package includes a first semiconductor die surrounded by a molding compound. The semiconductor package further includes a first conductive pad on the first semiconductor die, wherein the first conductive pad is at a top metal level of the first semiconductor die. The semiconductor package further includes redistribution lines (RDLs) formed over the first conductive pad, wherein at least one RDL of the RDLs extends beyond the boundaries of the semiconductor die, and a portion of the at least one RDL contacts the first conductive pad, wherein a surface of the first conductive pad contacting the portion of the at least one RDL is at a different level than a surface of the molding compound under the at least one RDL extended beyond the boundaries of the first semiconductor die.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung
  • Semiconductor package structure and manufacturing method thereof
    Patent number: 9997471
    Abstract: A semiconductor package structure includes a redistribution layer (RDL), a chip, a plurality of interconnecting bumps and an encapsulant. The redistribution layer has a first surface and a second surface opposite to each other. The chip is disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer. The interconnecting bumps are disposed over the first surface and electrically connected to the redistribution layer. The encapsulant is disposed over the first surface of the redistribution layer, and the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jui-Pin Hung, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, De-Dui Marvin Liao