Patents by Inventor Jui-Pin Hung

Jui-Pin Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect Structure for Package-on-Package Devices and a Method of Fabricating
    Publication number: 20170025397
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 26, 2017
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Interconnect structure for wafer level package
    Patent number: 9553000
    Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng
  • SEMICONDUCTOR PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170011981
    Abstract: A method of manufacturing a semiconductor device including providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing a conductive material on the pad within the opening.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Inventors: NAI-WEI LIU, JUI-PIN HUNG, JING-CHENG LIN
  • Methods of Packaging Semiconductor Devices and Structures Thereof
    Publication number: 20160343615
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • METHOD OF FORMING A SEMICONDUCTOR PACKAGE
    Publication number: 20160336280
    Abstract: A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.
    Type: Application
    Filed: July 26, 2016
    Publication date: November 17, 2016
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer
    Publication number: 20160329307
    Abstract: A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.
    Type: Application
    Filed: July 20, 2016
    Publication date: November 10, 2016
    Inventors: Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Die package with Openings Surrounding End-portions of Through Package Vias (TPVs) and Package on Package (PoP) Using the Die Package
    Publication number: 20160307778
    Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs. The openings surrounding the end-portions of the TPVs of the die package enable solders of the bonding structures formed between another die package to remain in the openings without sliding and consequently increases yield and reliability of the bonding structures. Polymers may also be added to fill the openings surrounding the TPVs or even the space between the die packages to reduce cracking of the bonding structures under stress.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Li-Hui Cheng
  • Semiconductor package device and manufacturing method thereof
    Patent number: 9466581
    Abstract: A semiconductor device includes a die, a pad disposed on the die and configured to be electrically coupled with a bump through a conductive trace attached on the pad, a polymer disposed over the die and patterned to provide a path for the conductive trace passing through, and a molding surrounding the die and the polymer. A top surface of the molding is substantially in a same level as a top surface of the polymer.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: October 11, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
  • Chip on Package Structure and Method
    Publication number: 20160293577
    Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.
    Type: Application
    Filed: June 20, 2016
    Publication date: October 6, 2016
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Kuo-Chung Yee, Jui-Pin Hung
  • Integrated Circuit Structure and Method of Forming
    Publication number: 20160295700
    Abstract: An integrated circuit structure and method of forming is provided. A die is place on a substrate and encased in molding compound. A redistribution layer is formed overlying the die and the substrate is removed. One or more surface mounted devices and/or packages are connected to the redistribution layer on an opposite side of the redistribution layer from the die. The redistribution layer is connected to a printed circuit board.
    Type: Application
    Filed: October 30, 2015
    Publication date: October 6, 2016
    Inventors: Chen-Hua Yu, Jui-Pin Hung, Kuo-Chung Yee
  • Interconnect structure for package-on-package devices and a method of fabricating
    Patent number: 9460987
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Package on Package (PoP) Bonding Structures
    Publication number: 20160284677
    Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures.
    Type: Application
    Filed: June 9, 2016
    Publication date: September 29, 2016
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Po-Hao Tsai
  • Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices
    Publication number: 20160276278
    Abstract: Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads.
    Type: Application
    Filed: May 27, 2016
    Publication date: September 22, 2016
    Inventors: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160268214
    Abstract: A semiconductor structure includes a plurality of devices; a molding surrounding the plurality of devices and including a first surface adjacent to an active component of at least one of the plurality of devices and a second surface opposite to the first surface; and a shielding structure disposed within the molding and between two or more of the plurality of devices, wherein the shielding structure includes a first surface adjacent to the first surface of the molding and a second surface adjacent to the second surface of the molding, and the second surface of the shielding structure includes a recessed portion recessed towards the first surface of the molding.
    Type: Application
    Filed: March 11, 2015
    Publication date: September 15, 2016
    Inventors: CHEN-HUA YU, MING-DA CHENG, JUI-PIN HUNG
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160254229
    Abstract: A semiconductor structure includes a plurality of devices, each of the plurality of devices includes a first surface disposed with an active component; and a molding disposed between the plurality of devices and including a first surface, wherein one of the plurality of devices has substantially different height from another one of the plurality of devices, and the first surface of the molding includes a recessed portion recessed from one of the first surfaces of the plurality of devices.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: CHEN-HUA YU, KUO-CHUNG YEE, JUI-PIN HUNG
  • Method of forming a semiconductor package
    Patent number: 9431367
    Abstract: A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • Integrated fan-out structure with guiding trenches in buffer layer
    Patent number: 9425121
    Abstract: A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Methods of packaging semiconductor devices and structures thereof
    Patent number: 9406581
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Package with a fan-out structure and method of forming the same
    Patent number: 9406598
    Abstract: An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Jui-Pin Hung, Jing-Cheng Lin
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON PLUGS
    Publication number: 20160197014
    Abstract: A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Chen-Hua YU, Hung-Pin CHANG, Yung-Chi LIN, Chia-Lin YU, Jui-Pin HUNG, Chien Ling HWANG