Patents by Inventor Jui-Pin Hung

Jui-Pin Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure and manufacturing method thereof
    Patent number: 9985006
    Abstract: The present disclosure provides a method of manufacturing a structure. The method comprises: providing a substrate; forming an interconnect layer over the substrate; forming a plurality of conductive pads over the interconnect layer; forming conductive pillars over the interconnect layer; disposing a first semiconductor die over the conductive pads, the semiconductor die being spaced apart from the conductive pillars; and bonding a second semiconductor die with the conductive pillars.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: May 29, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Puu Jeng, Jui-Pin Hung, Feng-Cheng Hsu
  • Semiconductor package device and manufacturing method thereof
    Patent number: 9978657
    Abstract: A method of manufacturing a semiconductor device including providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing a conductive material on the pad within the opening.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
  • Method of forming a semiconductor package
    Patent number: 9960125
    Abstract: A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • End point detection in grinding
    Patent number: 9960088
    Abstract: A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Jui-Pin Hung, Jing-Cheng Lin, Shin-Puu Jeng, Chen-Hua Yu
  • Integrated fan-out package structures with recesses in molding compound
    Patent number: 9953955
    Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Molding chamber apparatus and curing method
    Patent number: 9950450
    Abstract: An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Shin-Puu Jeng, Jui-Pin Hung, Hsien-Wen Liu
  • Three-layer Package-on-Package structure and method forming same
    Patent number: 9935080
    Abstract: A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of redistribution lines, and bonding a first device die to the first plurality of redistribution lines. The first metal post and the first device die are encapsulated in a first encapsulating material. The first encapsulating material is then planarized. The method further includes forming a second metal post over and electrically connected to the first metal post, attaching a second device die to the first encapsulating material through an adhesive film, encapsulating the second metal post and the second device die in a second encapsulating material, planarizing the second encapsulating material, and forming a second plurality of redistributions over and electrically coupling to the second metal post and the second device die.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Feng-Cheng Hsu, Shin-Puu Jeng
  • Interconnect structure for package-on-package devices and a method of fabricating
    Patent number: 9922903
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Integrated passive device package and methods of forming same
    Patent number: 9911629
    Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Jui-Pin Hung, Shin-Puu Jeng
  • SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20180033770
    Abstract: A semiconductor package structure includes an encapsulant, a first chip, a second chip, a first redistribution layer and a second redistribution layer. The encapsulant has a first surface and a second surface opposite to each other. The first chip is in the encapsulant, wherein the first chip includes a plurality of contact pads exposed from the first surface of the encapsulant. The second chip is in the encapsulant, wherein second chip includes a plurality of contact pads exposed from the second surface of the encapsulant. The first redistribution layer is over the first surface of the encapsulant and electrically connected to the contact pads of the first chip. The second redistribution layer is over the second surface of the encapsulant and electrically connected to the contact pads of the second chip.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 1, 2018
    Inventors: FENG-CHENG HSU, SHUO-MAO CHEN, JUI-PIN HUNG, SHIN-PUU JENG
  • SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180025992
    Abstract: A semiconductor package structure includes a redistribution layer (RDL), a chip, a plurality of interconnecting bumps and an encapsulant. The redistribution layer has a first surface and a second surface opposite to each other. The chip is disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer. The interconnecting bumps are disposed over the first surface and electrically connected to the redistribution layer. The encapsulant is disposed over the first surface of the redistribution layer, and the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps.
    Type: Application
    Filed: December 7, 2016
    Publication date: January 25, 2018
    Inventors: JUI-PIN HUNG, FENG-CHENG HSU, SHUO-MAO CHEN, SHIN-PUU JENG, DE-DUI MARVIN LIAO
  • SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20170373039
    Abstract: The present disclosure provides a semiconductor including a first semiconductor die layer having an active surface, a conductive contact electrically coupled to the active surface, a sidewall of the conductive contact being surrounded by an. insulating layer, and a solder bump connected to the conductive contact. A seed layer s between the sidewall of the conductive contact and the insulating layer. The present disclosure provides a method for manufacturing a semiconductor package, the method including providing a carrier, forming an insulating layer over the carrier, debonding the carrier from the insulating layer, and exposing the conductive contact from the insulating layer by an etching operation.
    Type: Application
    Filed: August 17, 2016
    Publication date: December 28, 2017
    Inventors: FENG-CHENG HSU, JUI-PIN HUNG, SHIN-PUU JENG
  • SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20170365587
    Abstract: The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged die having a carrier surface and a molding surface, and a first die structure in proximity to the carrier surface. An active region of the first die structure is electrically coupled to the packaged die through a solder. The second layer includes a second die structure, the second die structure being connected to the active region of the first die structure by a first redistributed layer (RDL). The conductive array is connected to an active region of the second die structure by a second RDL. The present disclosure also provides a method for manufacturing the aforesaid semiconductor package.
    Type: Application
    Filed: December 6, 2016
    Publication date: December 21, 2017
    Inventors: JUI-PIN HUNG, FENG-CHENG HSU, SHUO-MAO CHEN, SHIN-PUU JENG
  • Packages, packaging methods, and packaged semiconductor devices
    Patent number: 9847315
    Abstract: Packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a redistribution layer (RDL) and a plurality of through package vias (TPV's) coupled to the RDL. Each of the plurality of TPV's comprises a first region proximate the RDL and a second region opposite the first region. The first region comprises a first width, and the second region comprises a second width. The second width is greater than the first width.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Ting Lin, Szu Wei Lu, Jui-Pin Hung, Jing-Cheng Lin
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170345804
    Abstract: The present disclosure provides a method of manufacturing a structure. The method comprises: providing a substrate; forming an interconnect layer over the substrate; forming a plurality of conductive pads over the interconnect layer; forming conductive pillars over the interconnect layer; disposing a first semiconductor die over the conductive pads, the semiconductor die being spaced apart from the conductive pillars; and bonding a second semiconductor die with the conductive pillars.
    Type: Application
    Filed: December 7, 2016
    Publication date: November 30, 2017
    Inventors: SHIN-PUU JENG, JUI-PIN HUNG, FENG-CHENG HSU
  • Three-Layer Package-on-Package Structure and Method Forming Same
    Publication number: 20170317053
    Abstract: A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of redistribution lines, and bonding a first device die to the first plurality of redistribution lines. The first metal post and the first device die are encapsulated in a first encapsulating material. The first encapsulating material is then planarized. The method further includes forming a second metal post over and electrically connected to the first metal post, attaching a second device die to the first encapsulating material through an adhesive film, encapsulating the second metal post and the second device die in a second encapsulating material, planarizing the second encapsulating material, and forming a second plurality of redistributions over and electrically coupling to the second metal post and the second device die.
    Type: Application
    Filed: July 5, 2016
    Publication date: November 2, 2017
    Inventors: Jui-Pin Hung, Feng-Cheng Hsu, Shin-Puu Jeng
  • Chip on Package Structure and Method
    Publication number: 20170309596
    Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Kuo-Chung Yee, Jui-Pin Hung
  • Multi-Chip Fan Out Package and Methods of Forming the Same
    Publication number: 20170294409
    Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Jui-Pin Hung
  • Molding Wafer Chamber
    Publication number: 20170278723
    Abstract: A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung, Szu-Wei Lu, Shin-Puu Jeng, Chen-Hua Yu
  • Package on Package (PoP) Bonding Structures
    Publication number: 20170271311
    Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures.
    Type: Application
    Filed: June 6, 2017
    Publication date: September 21, 2017
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Po-Hao Tsai