Abstract: A semiconductor device is provided including NS-FETs in which the active area module, the shallow trench isolation module and the gate module are eliminated from the processing of the semiconductor device. The elimination of these modules makes the overall process easier and aids in reducing the cost of manufacturing the semiconductor device.

Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.

Abstract: Embodiments of the invention include a semiconductor structure having nanosheets separated by inner spacers, the inner spacers having a curved portion in a dimension. The semiconductor structure includes source/drain regions formed adjacent to the nanosheets and gate material formed on the nanosheets.

Abstract: A semiconductor integrated circuit (IC) device that includes an angled gate cut region, a first transistor associated with a first gate, and a second transistor associated with a second gate. The angled gate cut region may be angled such that its top surface area is nearest a boundary of the first transistor and its bottom surface area is nearest a boundary of the second transistor. The angled gate cut region may separate the first gate from the second gate and may further separate the source/drain regions of the first transistor from the source/drain regions of the second transistor. The angled gate cut region may provide for adequate frontside surface area of the first gate to which a frontside gate contact may connect and may further provide for adequate backside surface area of the second gate to which a backside gate contact may connect.

Abstract: The present disclosure describes an illustrative semiconductor IC device that includes a integrated logic microdevice and a memory microdevice that share the same vertical channel. By utilizing the same vertical channel, the overall footprint area of the integrated logic microdevice and the memory microdevice is relatively reduced and allows for further scaling of the associated semiconductor IC device.

Abstract: A SRAM is provided that includes a first pull-up transistor having a first channel length, and a first pull-down transistor located adjacent to the first pull-up transistor and having a second channel length, wherein the second channel length is greater than the first channel length. The structure further includes a first backside contact structure contacting a first n-doped source/drain region of the first pull-down transistor, wherein the first backside contact structure has a first critical dimension that is constant throughout an entirety thereof, and a second backside contact structure having a vertical portion and a base portion. The vertical portion of the second backside contact structure directly contacts a first p-doped source/drain region of the first pull-up transistor and the base portion of the second backside contact structure has a second critical dimension that is greater than the first critical dimension.

Abstract: A method to co-integrate a metal trench cut for aggressively scaled contact tip-to-tip and wrap-around-contact formation is provided. A semiconductor device made from the method is also provided in which a metal trench cut region and wrap-around-contacts are present.

Abstract: A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.

Abstract: A semiconductor structure for a phase-change memory device includes a heater element on a portion of a bottom electrode in a first dielectric material. The semiconductor structure includes a layer of phase-change material that surrounds a portion of a second dielectric material, where the layer of phase-change material forms a three-dimensional shape around the portion of the second dielectric material. A conductive liner is under a first portion of the layer of phase-change material and surrounds a portion of a bottom surface of a hardmask layer and vertical portions of the hardmask layer. A conductive material is on a portion of a top surface of the second dielectric material and abuts the vertical portions of the layer of phase-change material below the conductive liner and the hardmask layer. A top electrode is on a top surface of the conductive material.

Abstract: A semiconductor device includes a plurality of field effect transistors (FET) formed upon semiconductor fins. Each FET includes a gate disposed transversely upon a first portion of the fins of the FET, one or more source/drain regions disposed upon the fins and in contact with the gate, and an electrically isolating layer disposed adjacent to a second portion of the fins above the gate and the source/drain regions, the electrically isolating layer having an interface with the gate. The device further includes a buried power rail (BPR) disposed between otherwise adjacent FETs. The BPR includes a metal rail extending beyond the interface into the gate, and electrically isolating sidewalls separating the metal rail from the gate and the source/drain regions. The device also includes a via-buried power rail contact disposed adjacent to the electrically isolating sidewalls, in contact with the metal rail, and in contact with one source/drain region.

Abstract: A set of stacked transistors, system, and method to connect the gates of stacked field-effect transistors through sidewall straps. The set of stacked transistors may include a first transistor including a first gate. The set of stacked transistors may also include a second transistor including a second gate, where the second transistor is above the first transistor. The set of stacked transistors may also include a dielectric preventing direct contact between the first gate and the second gate. The set of stacked transistors may also include a first sidewall strap proximately connected to the first gate and the second gate, where the first sidewall strap connects the first transistor and the second transistor.

Abstract: A semiconductor device that includes a stack of nanostructure material layers overlying a substrate, wherein a gate all around structure is present on a channel region portion for the stack of nanostructure material layers. A bottom source and drain region is present on a first side of the channel region portion, wherein the bottoms source and drain region is composed by a first epitaxial semiconductor material that has a confinement sidewall spacer in direct contact with sidewalls of the first epitaxial semiconductor material defining a lateral dimension for the epitaxial semiconductor material. An upper source and drain region is present on a second side of the channel region portion for the stack of nanostructure material layers. The upper source and drain region is composed of a second epitaxial semiconductor material that partially extends over the confinement sidewall spacer.

Abstract: A semiconductor device that includes a stack of nanostructure material layers overlying a substrate, wherein a gate all around structure is present on a channel region portion for the stack of nanostructure material layers, and source and drain semiconductor contacts on each side of the gate all around structure. The source and drain semiconductor contacts are in direct contact with edges of the channel region portion for the stack of nanostructure material layers. A gate spacer between the source and drain semiconductor contacts and the gate all around structure. An electrically insulating substrate isolation layer aligned to be between the gate all around structure, the gate spacer and the substrate. A base portion of the gate spacer has an L-shaped geometry including a portion that warps over an upper surface of the electrically insulating substrate isolation layer.

Abstract: Provided is a reconfigurable Ring Oscillator (RO) Physical Unclonable Function (PUF), which comprises a NAND gate with a first input line and a second input line and a series of inverters with at least one memory cell placed between two inverters of the series of inverters, where an output of a last inverter provides input to the second input line, and where the memory cell comprises a Field Effect Transistor (FET). In addition, the reconfigurable RO PUF comprises a frequency counter, where the output of the last inverter provides input to the frequency counter. In normal operation mode, the first input line is on to enable ring oscillation and the FET is off. In reconfiguration mode, the first input line is off and the FET is on to enable reconfiguration.

Abstract: A device includes a plurality of magnetic random-access memory (MRAM) cells in a first region of the device; and a dummy MRAM pillar disposed in a second region of the device, wherein the dummy MRAM pillar is not connected to an active metal feature.

Abstract: According to the embodiment of the present invention, a semiconductor device includes a plurality of nanodevices including a plurality of transistors. The plurality of nanodevices are located adjacent to and parallel to each other along an x-axis. A gate contact is located at an edge of a cell boundary between two nanodevices of the plurality of nanodevices. The gate contact includes a recessed portion. A backside gate cut dielectric pillar extends downwards through the recessed portion to be in direct contact with the gate contact.

Abstract: A stacked device is provided. The stacked device includes a plurality of dielectric support bridges on a substrate, and a first two-dimensional (2D) channel layer on each of the plurality of dielectric support bridges. The stacked device further includes a gate dielectric sheet on the first two-dimensional (2D) channel layer, and a second two-dimensional (2D) channel layer on the first two-dimensional (2D) channel layer. The stacked device further includes a second gate dielectric layer on the gate dielectric sheets.

Abstract: A memory device that includes an magnetoresistive random-access memory (MRAM) stack positioned on an electrode, a metal line in contact with the electrode, and a sidewall spacer abutting the MRAM stack. The memory device also includes a stepped reach through conductor having a first height portion of the stepped reach through conductor in an undercut region positioned between the sidewall spacer and the metal line, and a second height portion having a greater height dimensions than the first height portion abutting an outer sidewall of the sidewall spacer.

Abstract: A semiconductor device comprises a first nanosheet transistor disposed on a semiconductor substrate, the first nanosheet transistor comprising a plurality of first gate structures, and a second nanosheet transistor disposed on the semiconductor substrate, the second nanosheet transistor comprising a plurality of second gate structures. Respective stacked spacer structures are disposed on respective sides of respective ones of the plurality of second gate structures, wherein each of the respective stacked spacer structures comprises a first spacer and a second spacer. Respective ones of the plurality of first gate structures comprise a first nanosheet gate portion and a gate dielectric layer around the first nanosheet gate portion. The respective ones of the plurality of second gate structures comprise a second nanosheet gate portion and at least two gate dielectric layers around the second nanosheet gate portion.

Abstract: Embodiments of the invention include a semiconductor structure having a first transistor having first nanosheets as first channel regions, a second transistor having second nanosheets as second channel regions, and a third transistor having third nanosheets as third channel regions. The first, second, and third nanosheets are formed of nanosheet material, where the first nanosheets are fewer in number than the second nanosheets. The semiconductor structure includes first end portions formed of the nanosheet material between first inner spacers in the first transistor. The first end portions are opposite one another and discontinuous in the first transistor.