Abstract: Embodiments of the invention are directed to an integrated circuit (IC) that includes a stacked device configuration having a top electronic device positioned over a bottom electronic device, along with an isolation region operable to electrically isolate at least a gate region of the top electronic device from a gate region of the bottom electronic device. The gate region of the top electronic device includes a first conductive material, and the gate region of the bottom electronic device includes a second conductive material that is different from the first conductive material.

Abstract: A semiconductor device includes a vertical insulator pillar extending from the substrate. A first stack of horizontal sheets of a first channel device is coupled to a lateral first side of the vertical insulator pillar and a second stack of horizontal sheets of a second channel device is coupled to a lateral second side of the vertical insulator pillar, opposite the first stack of horizontal sheets. A first gate stack is wrapped around the first stack of horizontal sheets. A second gate stack is wrapped around the second stack of horizontal sheets. A first gate extension is coupled to a center portion of the first gate stack and extending laterally away from the second gate stack and a second gate extension is coupled to a center portion of the second gate stack and extending laterally away from the first gate stack.

Abstract: Semiconductor devices and methods of forming the same include a first device region, a second device region, and an inter-device dielectric spacer between the first device region and the second device region. The first device region includes a first device channel, a first-polarity work function metal layer on the first device channel, and a second-polarity work function metal layer on the first device channel. The second device region include a second device channel, and a second-polarity work function metal layer on the second device channel.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first recess partially through a substrate from a first side of the substrate, forming a dielectric layer in the first recess, forming a second recess partially through the dielectric layer from the first side of the substrate, and forming a buried power rail (BPR) in the second recess of the dielectric layer. The method also includes thinning the substrate from a second side of the substrate to a level of the dielectric layer, the second side of the substrate being opposite to the first side of the substrate.

Abstract: A microelectronic device including a first nanosheet transistor includes a first source/drain and a second nanosheet transistor includes a second source/drain. The first source/drain and the second source/drain are adjacent to each other. Each of the first source/drain and the second source/drain have an asymmetrical profile when cut through the first and second source/drain.

Abstract: A transistor structure including a gate with a dielectric gate cap, a self-aligned source drain contact, where a topmost surface of the self-aligned source drain contact is substantially flush with a topmost surface of a first dielectric layer, a gate contact extending through the first dielectric layer, where a topmost surface of the gate contact is substantially flush with a topmost surface of a second dielectric layer, and a spacer surrounding the gate contact and physically separating it from the self-aligned source drain contact.

Abstract: A three-dimensional semiconductor structure with a bottom electrode in an interlayer dielectric material. The bottom electrode material with a rectangular shape has a first notch is in a top portion of a portion of the bottom electrode material. The first notch occurs in an intersection of the bottom electrode material with a top electrode material. A dielectric material contacts the bottom electrode material and a top surface of the interlayer dielectric material. The dielectric material is between five sides of the bottom electrode material and the top electrode material in the intersection of the bottom electrode material with the top electrode material and has a large contact area with of the bottom electrode material and the top electrode. When the bottom electrode material is a word line and the top electrode material is a bit line, the three-dimensional structure is a ReRAM cross point cell.

Abstract: A semiconductor structure including first metal lines embedded in a first dielectric layer, second metal lines embedded in a second dielectric layer, where the second metal lines arranged above the first metal lines, a top via extending between one of the first metal lines and one of the second metal lines, where the top via is self-aligned to the one of the first metal lines, and at least one air gap located adjacent to the top via between the first metal lines and the second metal lines.

Abstract: A semiconductor device includes a semiconductor substrate, a first pair of FET (field effect transistor) gate structures separated by a first gate canyon having a first gate canyon spacing, disposed upon the semiconductor substrate, a second pair of FET gate structures separated by a second gate canyon having a second gate canyon spacing, disposed upon the substrate, a first S/D (source/drain region disposed in the first gate canyon, a second S/D region disposed in the second gate canyon, a first BDI (bottom dielectric isolation) element disposed below the first S/D region and having a first BDI thickness, and a second BDI element disposed below the second S/D region and having a second BDI thickness. The first BDI thickness exceeds the second BDI thickness.

Abstract: A microelectronic device including a nanosheet transistor that includes a source/drain. At least a first and a second dielectric shoulders located on top of the source/drain and the at least the first and second dielectric shoulders are located at a permitter of the source/drain. The source/drain includes a gouged area located at a center of the source/drain. A source/drain contact connected to the source/drain, where the source/drain contact is in contact with a top surface the first dielectric shoulder. The source/drain contact includes a protrusion that extends into the source/drain, and the source/drain contact protrusion is located within the gouged area of the source/drain.

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.

Abstract: A complementary metal-oxide semiconductor device formed by fabricating CMOS nanosheet stacks, forming a dielectric pillar dividing the CMOS nanosheet stacks, forming CMOS FET pairs on either side of the dielectric pillar, and forming a gate contact for at least one of the FETs.

Abstract: A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions.

Abstract: A semiconductor device includes a bottom device, a top device, and a spacer. The bottom device includes a first set of silicon sheets and a first source-drain epitaxy in direct contact with the first set of silicon sheets. The top device includes a second set of silicon sheets, a set of separation layers, and a second source-drain epitaxy. Each silicon sheet of the second set of silicon sheets is separated by a separation layer of the set of separation layers. The second source-drain epitaxy is arranged in direct contact with the second set of silicon sheets. The spacer is arranged between the first source-drain epitaxy and the second source-drain epitaxy and is arranged between each silicon sheet of the second set of silicon sheets.

Abstract: A semiconductor structure includes a substrate and a gate-all-around field effect transistor disposed over the substrate. The gate-all-around field effect transistor includes a first source-drain region; a second source-drain region; at least one channel region interconnecting the first and second source drain regions; and a gate structure surrounding the at least one channel region. A self-aligned substrate isolation (SASI) layer is located between the substrate and the gate structure and extends over a width of the gate structure.

Abstract: A finFET that includes a nonlinear channel is presented. The nonlinear channel includes one or more arced, curved, segmented, or the like, sidewall(s) that define a channel width and a channel length. The nonlinear channel provides a relatively increased channel length compared to a linear fin that is orientated orthogonal to the gate width. As such, channel length of the nonlinear channel may be relatively increased within the confines of the gate. In other words, short channel effects may be limited due to a reduced electric field along the nonlinear channel due to the relatively increased channel or fin length within the footprint of the gate.

Abstract: A semiconductor structure includes an access transistor, a first memory device connected to a first side of the access transistor, and a second memory device connected to a second side of the access transistor. In some embodiments, the first memory device is connected to a first end of a first source/drain region of the access transistor and the second memory device is connected to a second end of the first source/drain region of the access transistor. In other embodiments, the first memory device is connected to a first source/drain region of the access transistor and the second memory device is connected to a second source/drain region of the access transistor.

Abstract: Semiconductor structures are disclosed which comprise semiconductor devices having buried power rails. In one example, a semiconductor structure comprises a plurality of semiconductor devices. Each of the semiconductor devices is isolated from an adjacent semiconductor device by a dielectric layer. The semiconductor structure further comprises a first diffusion break extending across the plurality of semiconductor devices, a second diffusion break extending across the plurality of semiconductor devices and a plurality of gates extending across the plurality of semiconductor devices. The gates are disposed between the first diffusion break and the second diffusion break. Each semiconductor device comprises a power rail extending between the first diffusion break and the second diffusion break under the plurality of gates.

Abstract: An integrated circuit has a frontside and a backside and includes a first CMOS cell of complementary metal oxide semiconductor (CMOS) devices. A first row of gate cuts and a second row of gate cuts bound the first CMOS cell. A gate is associated with at least one of the devices in the first CMOS cell. A first signal line is at the frontside of the integrated circuit. A signal connection is provided from the first signal line to the backside of the integrated circuit. A local interconnect is provided at the backside of the integrated circuit from the signal connection to the gate.

Abstract: A semiconductor device includes a magneto-resistive random access memory (MRAM) formed at a backside of a wafer. A self-aligning micro stud and silicide layer can directly electrically connect the MRAM to a source/drain (S/D) of a transistor in the MRAM region of the semiconductor device.