Abstract: Semiconductor structures having an increased gate length are provided by providing a vertical stack of suspended semiconductor channel material nanosheets that include a middle portion located between a first end portion and a second end portion. The middle portion of each suspended semiconductor channel material nanosheet is vertically offset from (i.e., higher or lower than) the first end portion and the second end portion of each suspended semiconductor channel material nanosheet.

Abstract: A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width W1 and the first nanosheet is tapered in the X-direction to have a length L1. A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width W2 and the first nanosheet is tapered in the X-direction to have a length L2. Wherein the widths W1 and W2 are different from each other and the lengths L1 and L2 are different from each other and wherein the substrate includes a tapered surface in the Y-direction.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dynamic random-access-memory (DRAM), and the DRAM includes a vertical transistor and a nanosheet transistor, the vertical transistor being stacked on top of the nanosheet transistor, where a bottom source/drain of the vertical transistor is directly above and connected to a gate of the nanosheet transistor through a conductive via. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor apparatus includes a substrate; a central vertical pillar of dielectric material protruding upward from the substrate; a left plurality of semiconductor fins protruding horizontally from a left side of the central vertical pillar above the substrate; a right plurality of semiconductor fins protruding horizontally from a right side of the central vertical pillar opposite the left plurality of semiconductor fins; a gate stack surrounding the central vertical pillar and the left and right pluralities of semiconductor fins; and a bottom dielectric insulating layer protruding horizontally left and right of the central vertical pillar below the left and right pluralities of fins and adjacent to the substrate.

Abstract: Semiconductor structures including stacked transistors are provided. The semiconductor structures can include a pair of stacked forksheet transistors that have a shared second (top) gate electrode, or the structures can include a pair of stacked forksheet transistors that have non-shared second (top) gate electrodes. In either of these embodiments, the second (top) gate electrode is separated from a first (bottom) gate electrode by a frontside gate cut structure.

Abstract: Semiconductor devices includes a bottom field effect transistor (FET) over a substrate, having a bottom channel and bottom source/drain structures. A bottom plug of dielectric material penetrates the substrate and that makes contact with a channel of the bottom FET. A top FET over the bottom FET has a top channel that is laterally offset with respect to the bottom channel. Electrical contacts reach to the top FET and the bottom FET.

Abstract: A stacked transistor structure including a top source drain region above a bottom source drain region, wherein a width of the bottom source drain region is greater than a width of the top source drain region, a bottom contact structure directly above and in electrical contact with the bottom source drain region, a replacement spacer surrounding the bottom contact structure, and a top gate spacer separating the replacement spacer from a gate conductor.

Abstract: Semiconductor devices include transistors in an active layer. Top vias are in electrical contact between top surfaces of the transistors and overlying frontside back-end-of-line (BEOL) layers. A local interconnect is in electrical contact between transistors underneath the transistors. Bottom vias are in electrical contact between bottom surfaces of the transistors and underlying backside BEOL layers.

Abstract: A semiconductor structure including a first transistor having a first gate-to-gate space and a first source drain region, a second transistor having a second gate-to-gate space and a second source drain region, where the first gate-to-gate space is less than the second gate-to-gate space, and where a bottommost surface of the first source drain region is above a bottommost surface of the second source drain region.

Abstract: A semiconductor device comprises a plurality of gate structures stacked with a plurality of core channel layers comprising a first semiconductor material, and a plurality of cladding channel layers disposed around the plurality of gate structures and comprising a second semiconductor material different from the first semiconductor material. A source/drain region is disposed on a side of the plurality of gate structures and the plurality of core channel layers. Respective ones of a plurality of buffer semiconductor layers are disposed between respective ones of the plurality of core channel layers and the source/drain region.

Abstract: A semiconductor structure includes a first nanosheet field-effect transistor device having a plurality of first nanosheet channel layers disposed on a substrate, a second nanosheet field-effect transistor device adjacent the first field-effect transistor nanosheet device, the second field-effect transistor nanosheet device having a plurality of second nanosheet channel layers disposed on the substrate, a first source/drain region disposed between opposing sidewalls of the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers and extending into the substrate, and source/drain sidewall spacers disposed on sidewalls of the first source/drain region extending into the substrate.

Abstract: A semiconductor device includes at least one transistor including a gate structure and a source/drain region, and a source/drain contact structure disposed on the source/drain region. The source/drain contact structure includes a first metal layer and second metal layer disposed on the first metal layer, wherein the second metal layer includes a different material than the first metal layer and is disposed on an uppermost surface of the first metal layer. A gate cut portion is disposed through a part of the gate structure, wherein the source/drain contact structure is disposed on a side of the gate cut portion.

Abstract: A fin stack including compressively strained and tensile-strained semiconductor fin regions allows CMOS fabrication to form vertically stacked p-type FinFETs and n-type FinFETs. Aspect ratio trapping within a semiconductor base region within the fin stack provides a relaxed semiconductor base region on which uniaxially strained regions are grown. A dielectric layer may be formed to electrically isolate the compressively strained semiconductor fin region from the tensile-strained semiconductor fin region.

Abstract: A semiconductor structure is provided that has a lowered gate aspect ratio on the shallow trench isolation area to prevent gate structure flop over. The structure includes a shallow trench isolation region including a first trench dielectric material having a first height. The structure further includes an active device region located adjacent to the shallow trench isolation region. The active device region includes a second trench dielectric material having a second height which is less than the first height.

Abstract: A semiconductor structure includes a backside gate extension extending from a frontside gate region through a dielectric isolation layer, a backside gate contact partially disposed on the backside gate extension, and a backside interconnect connected to the backside gate extension by the backside gate contact.

Abstract: Embodiments of the present disclosure are directed to processing methods and resulting structures that leverage an angled epitaxy cut to provide an angled source/drain isolation pillar that optimizes contact size for both frontside contacts and backside contacts. In a non-limiting embodiment, a semiconductor device includes a first source or drain (S/D) region and a second S/D region. The semiconductor device further includes an angled isolation pillar between the first S/D region and the second S/D region.

Abstract: A semiconductor structure including a stacked forksheet FET is provided. The semiconductor structure includes a frontside gate cut structure that physically isolates a bottom forksheet FET from a top forksheet FET. The frontside gate cut structure provides a physical barrier that allows for a first metal gate electrode to be removed from the top forksheet FET without negatively impacting (i.e., removing) the first metal gate electrode of the bottom FET. After removal of the first metal gate electrode from the top forksheet FET, a second metal gate electrode can be formed in the area of the top forksheet FET which was previously occupied by the first metal gate electrode.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first source/drain (S/D) epitaxially grown in a device layer, a frontside contact contacting a frontside of the first S/D, a backside contact contacting a backside of the first S/D, and a via contact contacting: i) a sidewall of the first S/D, ii) the frontside contact, and iii) the backside contact.

Abstract: Embodiments are disclosed for a semiconductor structure that includes a first stacked field effect transistor (FET) configured as a shared gate device, and a second stacked FET configured to operate as two independent gate devices. The first stacked FET includes a first top FET having a first top work-function metal (WFM) and a first bottom FET having a first bottom WFM. Further, the first top WFM and the first bottom WFM are connected through shared gate connectors disposed on either side of a middle dielectric isolation (MDI) layer. Further, the second stacked FET includes a second top FET having a second top WFM and a second bottom FET having a second bottom WFM. Further, the second top WFM and the second bottom WFM are separated by the MDI layer and a pair of spacer shoulders disposed on either side of the MDI layer.

Abstract: A gate-all-around device includes a plurality of channel layers vertically stacked over a substrate, an inner spacer located between each of the plurality of channel layers, source/drain regions in contact with opposite ends of a first portion of the plurality of channel layers, and a first dielectric layer on opposite ends of a second portion of the plurality of channel layers located in a spacer region that is adjacent to the source/drain regions. A width of the first dielectric layer and the second portion of the plurality of channel layers is equal to a width of the inner spacer located between each of the plurality of channel layers.