Abstract: A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a source or drain (S/D) region. The FET also includes a backside S/D contact connected to a top surface of the S/D region. The backside S/D contact includes a lateral portion upon the top surface of the S/D region. The lateral portion further laterally extends adjacent to or past the first S/D region. The backside S/D contact includes a vertical portion that extends vertically downward from the lateral portion below the bottom surface of the substrate layer. The FET also includes a backside S/D mushroom that extends vertically downward from the vertical portion.

Abstract: A semiconductor structure includes a source/drain region having a backside surface disposed in a backside interlayer dielectric layer, a backside contact disposed in the backside interlayer dielectric layer, wherein the backside contact is disposed on the backside surface of the source/drain region, backside sidewall spacers disposed between sidewalls of the backside interlayer dielectric layer and sidewalls of the backside contact and the backside surface of the source drain region, and a backside power rail connected to the source/drain region through the backside contact.

Abstract: A semiconductor structure is provided that includes a backside bitline connected to a dynamic random access memory (DRAM) cell that includes a plurality of field effect transistors (FETs) and a plurality of DRAM capacitors that are present in a frontside of the structure.

Abstract: A semiconductor structure comprises a source/drain region, a spacer layer on a first side of the source/drain region, a contact on a top surface of the source/drain region, and a via connected to a portion of the contact at a second side of the source/drain region, the second side of the source/drain region being opposite the first side of the source/drain region.

Abstract: A deep-via structure includes at least one via-interfacing layer. The deep-via structure also includes a via. The via is embedded within the at least one via-interfacing layer. The via includes a conductive material. The deep-via structure also includes a stress-relief void that is formed within the conductive material of the via.

Abstract: A semiconductor structure includes a first transistor device, a second transistor device, and a dielectric pillar structure disposed between the first transistor device and the second transistor device. The dielectric pillar structure includes a first dielectric pillar adjacent the first transistor device and a second dielectric pillar adjacent the second transistor device.

Abstract: Embodiments of the invention include an isolation layer under a nanosheet stack of a transistor and a graded layer under the isolation layer. The graded layer includes an impurity gradient.

Abstract: Embodiments of the invention include a transistor comprising a gate region and a source/drain region. A first isolation layer is under the gate region. A second isolation layer is separated from the first isolation layer by a third isolation layer.

Abstract: A semiconductor structure including a stacked transistor structure comprising a top device stacked directly above a bottom device, and a bilayer gate dielectric layer separating the top device from the bottom device.

Abstract: A device structure for a phase-change memory device is disclosed. The device structure includes a top electrode, a phase-change material that is recessed between two layers of resistive liner material, and a conductive material. The conductive material contacts the sidewall of the top electrode, the sidewall of the phase-change material, and a portion of a top surface and a bottom surface of each of the two layers of the resistive liner material. The device structure includes a heater contacting a bottom electrode and the bottom layer of the resistive liner material. The heater is in a first bilayer dielectric. A second bilayer dielectric is under the top electrode.

Abstract: A semiconductor device includes a field effect transistor (FET) with at least one Gate-All-Around (GAA) channel. A first conductive ferromagnetic Source/Drain contact is electrically connected with a first portion of the GAA channel. A second conductive ferromagnetic Source/Drain contact is electrically connected with a second portion of the GAA channel. A remanent magnetization of the first conductive ferromagnetic contact is oriented in a direction opposite to a remanent magnetization of the second conductive ferromagnetic contact.

Abstract: A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source/drain contact structure, and thus improves process margin.

Abstract: A semiconductor structure includes a backside contact, and an unmerged source/drain region. The backside contact is wrapped-around the unmerged source/drain region.

Abstract: A semiconductor structure includes a backside contact, and a source/drain region fully disposed within the backside contact.

Abstract: Embodiments of present invention provide a method of forming a phase change memory device. The method includes forming a bottom electrode on a supporting structure; forming a first blanket dielectric layer, a phase-change material layer, a second blanket dielectric layer, and a hard mask sequentially on top of the bottom electrode; forming an inner spacer in an opening in the hard mask to modify the opening; extending the opening into the second blanket dielectric layer to create an extended opening; filling the extended opening with a heating element; etching the second blanket dielectric layer, the phase-change material layer, and the first blanket dielectric layer respectively into a second dielectric layer, a phase-change element, and a first dielectric layer; forming a conductive liner surrounding the phase-change element; and forming a top electrode on top of the heating element. A structure formed thereby is also provided.

Abstract: A semiconductor structure is presented including a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers disposed on sidewalls of each FET device, second spacers disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and a gate contact directly contacting an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof. The second spacers can have a bi-layer configuration and the gate contact wraps around a top portion of the FET device in direct contact with the gate contact.

Abstract: A semiconductor structure comprises a first transistor, a second transistor vertically stacked over the first transistor, a source/drain region shared between the first transistor and the second transistor, and a resistive random-access memory device connected to the shared source/drain region.

Abstract: A semiconductor structure is provided that includes a pFET located in a pFET device region, the pFET includes a first functional gate structure and a plurality of pFET semiconductor channel material nanosheets, and an nFET located in the nFET device region, the nFET includes a second functional gate structure and a plurality of pFET semiconductor channel material nanosheets. The pFET semiconductor channel material nanosheets can be staggered relative to, or vertically aligned in a horizontal direction with, the nFET semiconductor channel material nanosheets. When staggered, a bottom dielectric isolation structure can be located in both the device regions, and the second functional gate structures has a bottommost surface that extends beneath a topmost surface of the bottom dielectric isolation structure. When horizontally aligned, a vertical dielectric pillar is located between the two device regions.

Abstract: A contact structure having reduced middle-of-the-line (MOL) resistance is provided that includes a source/drain contact which includes a liner and a via contact that is liner-less. The via contact includes a first via portion having a first critical dimension and a second via portion having a second critical dimension that is greater than the first critical dimension. The second critical dimension provides a maximized via contact bottom critical dimension over the source/drain contact, while the first critical dimension provides sufficient area between the first via portion of the via contact and a neighboring electrically conductive structure thus avoiding any shorts between those two elements.

Abstract: Embodiments of present invention provide a method of improving yield of making MRAM arrays. More specifically, the method includes receiving an MRAM array; identifying a weak MRAM cell from the MRAM array wherein the weak MRAM cell includes an access transistor; and modifying the access transistor. In one embodiment, modifying the access transistor includes performing a hot carrier injection into a gate dielectric layer of the access transistor.