Patents by Inventor Julien Frougier

Julien Frougier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • EMBEDDED ReRAM WITH BACKSIDE CONTACT
    Publication number: 20240196627
    Abstract: A semiconductor structure including a one-transistor one-capacitor (1T1R) device is provided that includes an embedded resistive random access memory (ReRAM) having a width larger than 1 gate pitch, that is present in a frontside or the backside of the structure, a frontside contact structure electrically connected to a source region of the transistor of the 1T1R device and a backside contact structure electrically connected to a drain region of the transistor of the 1T1R device.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 13, 2024
    Inventors: Min Gyu Sung, Julien Frougier, Ruilong Xie, Chanro Park, Juntao Li, Soon-Cheon Seo, Takashi Ando, Chen Zhang, Heng Wu
  • PREVENTING SOURCE/DRAIN EPI MERGE WITHOUT CELL SIZE INCREASE
    Publication number: 20240194677
    Abstract: A semiconductor device includes a first nanosheet field effect transistor (PET) having a first gate stack arranged on a substrate. A second nanosheet FET is arranged on the substrate adjacent to the first nanosheet FET. The second FET includes a second gate stack, wherein a top of the first gate stack and a top of the second gate stack have different heights.
    Type: Application
    Filed: December 10, 2022
    Publication date: June 13, 2024
    Inventors: Min Gyu Sung, Julien Frougier, Ruilong Xie, Chanro Park, Juntao Li
  • Integrated nanosheet field effect transistors and floating gate memory cells
    Patent number: 12009435
    Abstract: A semiconductor device including a nanosheet field effect transistor (FET) comprising a thin gate oxide layer and a floating gate memory cell comprising a tunneling oxide, a floating gate, and a blocking oxide layer over a fin FET device. The device fabricated by forming a nanosheet stack and fin structures, forming tunneling oxide and floating gate layers over the nanosheet stack and fin structures, forming dummy gate structures over the nanosheet stack and fin structures, removing the dummy gate structures, forming a blocking oxide layer over the floating gate, and forming replacement metal gates.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 11, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Alexander Reznicek
  • NANOSHEET METAL-INSULATOR-METAL CAPACITOR
    Publication number: 20240186317
    Abstract: A semiconductor device is provided. The semiconductor device includes: a first nanosheet device including a plurality of active semiconductor layers, a first metal stack wrapping around the active semiconductor layers, and a first gate insulator layer between the active semiconductor layers and the first metal stack; and a second nanosheet device including a second metal contact, the first metal stack wrapping around the second metal contact, and a second gate insulator between the second metal contact and the first metal stack.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 6, 2024
    Inventors: Ruilong Xie, Julien Frougier, Alexander Reznicek, Sagarika Mukesh
  • GATE-ALL-AROUND DEVICE WITHOUT DIELECTRIC INNER SPACER
    Publication number: 20240186391
    Abstract: A semiconductor structure includes a first gate-all-around device disposed on a first region of a substrate and a second gate-all-around device disposed on a second region of the substrate. The first gate-all-around device includes a first metal gate stack surrounding a first channel layer. The first metal gate stack is separated from a first source/drain region by a dielectric inner spacer disposed on opposite sides of the first metal gate stack. The second gate-all-around device includes a second metal gate stack surrounding a second channel layer. The second metal gate stack is separated from a second source/drain region by an epitaxial layer disposed on opposite sides of the second metal gate stack.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 6, 2024
    Inventors: Julien Frougier, Sung Dae Suk, Ruilong Xie, Christopher J. Waskiewicz, Veeraraghavan S. Basker
  • STACKED TRANSISTORS HAVING BOTTOM CONTACT WITH LARGER SILICIDE
    Publication number: 20240186325
    Abstract: A stacked transistor structure including a top source drain region above a bottom source drain region, where a width of the bottom source drain region is greater than a width of the top source drain region, a bottom contact structure directly above and in electrical contact with the bottom source drain region, a metal silicide between the bottom source drain region and the bottom contact structure, the metal silicide having a width larger than a width of the bottom contact structure; a replacement spacer surrounding the bottom contact structure; and a top gate spacer separating the replacement spacer from a gate conductor.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 6, 2024
    Inventors: Koichi Motoyama, Ruilong Xie, Julien Frougier, Nicolas Jean Loubet, Kangguo Cheng
  • STRUCTURE WITH FRONTSIDE AND BACKSIDE DRAMS
    Publication number: 20240188282
    Abstract: A semiconductor structure having a high cell density is provided in which a frontside dynamic access memory (DRAM) is located on a frontside of a semiconductor substrate, and a backside DRAM is located on a backside of the semiconductor substrate. Peripheral transistors can be located on the frontside of the semiconductor substrate and at a same level as frontside transistors of the frontside DRAM.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 6, 2024
    Inventors: Min Gyu Sung, Kangguo Cheng, Ruilong Xie, Chanro Park, Julien Frougier
  • VIA AND SOURCE/DRAIN CONTACT LANDING UNDER POWER RAIL
    Publication number: 20240186387
    Abstract: A microelectronic structure including a first nano device that includes a plurality of first transistors and the plurality of first transistors includes at least one first source/drain. A second nano device includes a plurality of second transistors and the second nano device is oriented parallel to the first nano device. The plurality of second transistors includes at least two second source/drains. A gate cut located between the first nano device and the second nano device. A source/drain contact connected to the at least one first source/drain and is connected to at least one of the second source/drains. A portion of the source/drain contact extends parallel to the first nano device and the second nano device.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 6, 2024
    Inventors: Ruilong Xie, Min Gyu Sung, Chanro Park, Kangguo Cheng, Julien Frougier
  • Dual dielectric pillar fork sheet device
    Patent number: 12002808
    Abstract: A forksheet transistor device includes a dual dielectric pillar that includes a first dielectric and a second dielectric that is different from the first dielectric. The dual dielectric pillar physically separates pFET elements from nFET elements. For example, the first dielectric physically separates a pFET gate from a nFET gate while the second dielectric physically separates a pFET source/drain region from a nFET source drain region. When it is advantageous to electrically connect the pFET gate and the nFET gate, the first dielectric may be etched selective to the second dielectric to form a gate connector trench within the dual dielectric pillar. Subsequently, an electrically conductive gate connector strap may be formed within the gate connector trench to electrically connect the pFET gate and the nFET gate.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 4, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Julien Frougier, Kangguo Cheng, Dimitri Houssameddine
  • Nanosheet-based semiconductor structure with dielectric pillar
    Patent number: 12002850
    Abstract: A semiconductor structure includes a substrate, a first device disposed on the substrate and a second device disposed on the substrate. The first device includes a first plurality of nanosheets comprising a p-type material. The second device includes a second plurality of nanosheets comprising an n-type material. A dielectric isolation pillar is disposed between the first device and the second device.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 4, 2024
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Julien Frougier, Ruilong Xie, Chanro Park
  • PHASE CHANGE MEMORY
    Publication number: 20240180047
    Abstract: An apparatus includes a substrate that has an upper face; a first electrode that is attached to the upper face of the substrate; a second electrode that is attached to the upper face of the substrate at a distance from the first electrode; and a bridge of phase-change-memory material that is attached to and lies along the upper face of the substrate between and electrically connecting the first and second electrodes. At least a portion of the bridge is thermally switchable between a low resistance solid phase and a high resistance solid phase. In some embodiments, the apparatus also includes access devices that are disposed between the electrodes and the substrate, with the bridge being electrically connected between the access devices. At least a portion of the bridge is thermally switchable between a low resistance solid phase and a high resistance solid phase.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventors: Kangguo Cheng, Juntao Li, Julien Frougier, Ruilong Xie
  • SUPPORT DIELECTRIC FIN TO PREVENT GATE FLOP-OVER IN NANOSHEET TRANSISTORS
    Publication number: 20240178156
    Abstract: One or more systems, devices, and/or methods of fabrication provided herein relate to nanosheet transistors with support dielectric pillars. According to one embodiment, a transistor device can comprise an active transistor fin and a support dielectric pillar located adjacent to the active transistor fin, wherein the support dielectric pillar stabilizes the active transistor fin.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Juntao Li, Min Gyu Sung, Ruilong Xie, Julien Frougier, Chanro Park
  • THREE DIMENSIONAL RERAM DEVICE
    Publication number: 20240179924
    Abstract: A resistive random access memory (ReRAM) device and a method for forming the device are provided. The ReRAM device includes a first electrode, a resistive switching element layer in contact with the first electrode, and a plurality of second electrodes in contact with the resistive switching element layer. Protruding portions of the first electrode and the resistive switching element layer overlap with the plurality of second electrodes in a vertical direction of the ReRAM device to form a plurality of vertically stacked ReRAM cells.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Inventors: Min Gyu Sung, Soon-Cheon Seo, Heng Wu, Julien Frougier, Chen Zhang, Ruilong Xie
  • LOCAL INTERCONNECT FORMATION AT DOUBLE DIFFUSION BREAK
    Publication number: 20240178136
    Abstract: A microelectronic structure including a first nano device that includes a plurality of first transistors and a second nano device that includes a plurality of second transistors. The first nano device and the second nano device are parallel to each other. A doubled diffusion break that extends across the first nano device and the second nano device. A back-end-of-the-line (BEOL) layer located on a frontside of the first nano device and the second nano device. A backside interconnect located on a backside of the first nano device and the second nano device and the BEOL layer is connected to the backside interconnect through the double diffusion break.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventors: Ruilong Xie, Min Gyu Sung, Julien Frougier, Chanro Park, Kangguo Cheng
  • SEMICONDUCTOR STRUCTURE WITH STRAINED NANOSHEET CHANNEL
    Publication number: 20240170538
    Abstract: A semiconductor structure includes a field-effect transistor region having a strained channel. The strained channel has a silicon germanium core layer and a silicon cladding layer disposed on the core layer.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 23, 2024
    Inventors: Liqiao Qin, Heng WU, Ruilong Xie, Julien Frougier, Min Gyu Sung, Shogo Mochizuki, Andrew M. Greene
  • CIRCUIT ARCHITECTURE USING TRANSISTORS WITH DYNAMIC DUAL FUNCTIONALITY FOR LOGIC AND EMBEDDED MEMORY DRIVERS
    Publication number: 20240172454
    Abstract: Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 23, 2024
    Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Heng Wu, Min Gyu Sung, Chanro Park
  • SEMICONDUCTOR STRUCTURE HAVING A BACKSIDE CONTACT WITH BACKSIDE SIDEWALL SPACERS
    Publication number: 20240154009
    Abstract: A semiconductor structure includes a source/drain region having a backside surface disposed in a backside interlayer dielectric layer, a backside contact disposed in the backside interlayer dielectric layer, wherein the backside contact is disposed on the backside surface of the source/drain region, backside sidewall spacers disposed between sidewalls of the backside interlayer dielectric layer and sidewalls of the backside contact and the backside surface of the source drain region, and a backside power rail connected to the source/drain region through the backside contact.
    Type: Application
    Filed: November 8, 2022
    Publication date: May 9, 2024
    Inventors: Tao Li, Julien Frougier, Min Gyu Sung, Ruilong Xie
  • FET DRAM WITH BACKSIDE BITLINE
    Publication number: 20240155826
    Abstract: A semiconductor structure is provided that includes a backside bitline connected to a dynamic random access memory (DRAM) cell that includes a plurality of field effect transistors (FETs) and a plurality of DRAM capacitors that are present in a frontside of the structure.
    Type: Application
    Filed: November 8, 2022
    Publication date: May 9, 2024
    Inventors: Min Gyu Sung, Julien Frougier, Ruilong Xie, Chanro Park
  • FIELD EFFECT TRANSISTOR WITH BACKSIDE SOURCE/DRAIN CONTACT
    Publication number: 20240153990
    Abstract: A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a source or drain (S/D) region. The FET also includes a backside S/D contact connected to a top surface of the S/D region. The backside S/D contact includes a lateral portion upon the top surface of the S/D region. The lateral portion further laterally extends adjacent to or past the first S/D region. The backside S/D contact includes a vertical portion that extends vertically downward from the lateral portion below the bottom surface of the substrate layer. The FET also includes a backside S/D mushroom that extends vertically downward from the vertical portion.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Inventors: Chanro Park, Ruilong Xie, Julien Frougier, Min Gyu Sung, Juntao Li
  • DEEP VIA WITH INTERNAL VOID FOR STRESS MITIGATION
    Publication number: 20240145407
    Abstract: A deep-via structure includes at least one via-interfacing layer. The deep-via structure also includes a via. The via is embedded within the at least one via-interfacing layer. The via includes a conductive material. The deep-via structure also includes a stress-relief void that is formed within the conductive material of the via.
    Type: Application
    Filed: November 1, 2022
    Publication date: May 2, 2024
    Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng