Patents by Inventor Julien Frougier

Julien Frougier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STRUCTURE AND METHOD TO FORM VIA TO BACKSIDE POWER RAIL WITHOUT SHORTING TO GATE TIP
    Publication number: 20240204008
    Abstract: One or more systems, devices and/or methods of fabrication provided herein relate to forming a via to backside power rail (VBPR) on a semiconductor device. According to one embodiment, a VBPR with a via spacer is formed before a late gate cut is performed to create a replacement metal gate (RMG), wherein the via spacer prevents a short circuit between the VBPR and the RMG. Further, the via spacer is removed in locations on the VBPR where a source/drain region is adjacent to the VBPR, allowing a conductive connection between the VBPR and the adjacent source/drain region.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 20, 2024
    Inventors: Chanro Park, Ruilong Xie, Min Gyu Sung, Julien Frougier, Juntao Li
  • TRANSISTORS WITH DIELECTRIC STACK ISOLATING BACKSIDE POWER RAIL
    Publication number: 20240204005
    Abstract: A semiconductor structure includes a frontside source/drain region, and a dielectric stack disposed on a bottom surface of the frontside source/drain region. The dielectric stack includes a first dielectric layer and a second dielectric layer.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Inventors: Tao Li, Sagarika Mukesh, Julien Frougier, Nicolas Jean Loubet, Ruilong Xie
  • SELF-ALIGNED GATE METAL WITH TOP-DIELECTRIC ISOLATION
    Publication number: 20240204079
    Abstract: A semiconductor device includes a substrate and a stack of nanosheets supported by the substrate. A plurality of semiconductor channels in the stack of nanosheets includes a top channel. A gate body is coupled to the top channel. The gate body includes a layer of metal positioned on top of the top channel. A spacer body includes a top dielectric layer positioned on top of the layer of metal. A thickness of the layer of metal above the top channel is based on a distance from a bottom surface of the top dielectric layer to a top surface of the top channel.
    Type: Application
    Filed: December 17, 2022
    Publication date: June 20, 2024
    Inventors: Andrew Gaul, Julien Frougier, Ruilong Xie, Andrew M. Greene
  • GATE TIE-DOWN FOR TOP FIELD EFFECT TRANSISTOR
    Publication number: 20240203992
    Abstract: A semiconductor device is provided. The semiconductor device includes a stacked field effect transistor (FET) structure. The stacked FET structure includes a bottom FET device, a top FET device overlying the bottom FET device, dielectric material interposed between the bottom FET device and the top FET device and a gate tie-down assembly of the top FET device extending through the bottom FET device.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Inventors: Ruilong Xie, Julien Frougier, Min Gyu Sung, Chanro Park, Juntao Li
  • LOW-RESISTANCE VIA TO BACKSIDE POWER RAIL
    Publication number: 20240203879
    Abstract: Semiconductor devices and methods of forming the same include a front-end-of-line (FEOL) layer including a FEOL device. A backside power line is on a back side of the FEOL layer. A conductive structure contacts the FEOL device at a front side of the FEOL layer and extends through the FEOL layer to contact the backside power line. The conductive structure includes a frontside part that includes a metal liner and a first fill material and a backside part that includes a second fill material having an outer surface that aligns with an outer surface of the metal liner.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 20, 2024
    Inventors: Ruilong Xie, Julien Frougier, Chanro Park, Min Gyu Sung, Juntao Li
  • DIFFUSION BREAK STRUCTURE FOR TRANSISTORS
    Publication number: 20240204042
    Abstract: A semiconductor device includes a first gate region and a second gate region. A diffusion break region is between the first gate region and the second gate region. A top surface of the diffusion break region is co-planar with at least one of a top surface of one or more gate contacts and a top surface of one or more source/drain contacts.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Inventors: Ruilong Xie, Tao Li, Julien Frougier, Susan Ng Emans, Carl Radens, Dureseti Chidambarrao
  • EMBEDDED ReRAM WITH BACKSIDE CONTACT
    Publication number: 20240196627
    Abstract: A semiconductor structure including a one-transistor one-capacitor (1T1R) device is provided that includes an embedded resistive random access memory (ReRAM) having a width larger than 1 gate pitch, that is present in a frontside or the backside of the structure, a frontside contact structure electrically connected to a source region of the transistor of the 1T1R device and a backside contact structure electrically connected to a drain region of the transistor of the 1T1R device.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 13, 2024
    Inventors: Min Gyu Sung, Julien Frougier, Ruilong Xie, Chanro Park, Juntao Li, Soon-Cheon Seo, Takashi Ando, Chen Zhang, Heng Wu
  • PREVENTING SOURCE/DRAIN EPI MERGE WITHOUT CELL SIZE INCREASE
    Publication number: 20240194677
    Abstract: A semiconductor device includes a first nanosheet field effect transistor (PET) having a first gate stack arranged on a substrate. A second nanosheet FET is arranged on the substrate adjacent to the first nanosheet FET. The second FET includes a second gate stack, wherein a top of the first gate stack and a top of the second gate stack have different heights.
    Type: Application
    Filed: December 10, 2022
    Publication date: June 13, 2024
    Inventors: Min Gyu Sung, Julien Frougier, Ruilong Xie, Chanro Park, Juntao Li
  • Integrated nanosheet field effect transistors and floating gate memory cells
    Patent number: 12009435
    Abstract: A semiconductor device including a nanosheet field effect transistor (FET) comprising a thin gate oxide layer and a floating gate memory cell comprising a tunneling oxide, a floating gate, and a blocking oxide layer over a fin FET device. The device fabricated by forming a nanosheet stack and fin structures, forming tunneling oxide and floating gate layers over the nanosheet stack and fin structures, forming dummy gate structures over the nanosheet stack and fin structures, removing the dummy gate structures, forming a blocking oxide layer over the floating gate, and forming replacement metal gates.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 11, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Alexander Reznicek
  • NANOSHEET METAL-INSULATOR-METAL CAPACITOR
    Publication number: 20240186317
    Abstract: A semiconductor device is provided. The semiconductor device includes: a first nanosheet device including a plurality of active semiconductor layers, a first metal stack wrapping around the active semiconductor layers, and a first gate insulator layer between the active semiconductor layers and the first metal stack; and a second nanosheet device including a second metal contact, the first metal stack wrapping around the second metal contact, and a second gate insulator between the second metal contact and the first metal stack.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 6, 2024
    Inventors: Ruilong Xie, Julien Frougier, Alexander Reznicek, Sagarika Mukesh
  • GATE-ALL-AROUND DEVICE WITHOUT DIELECTRIC INNER SPACER
    Publication number: 20240186391
    Abstract: A semiconductor structure includes a first gate-all-around device disposed on a first region of a substrate and a second gate-all-around device disposed on a second region of the substrate. The first gate-all-around device includes a first metal gate stack surrounding a first channel layer. The first metal gate stack is separated from a first source/drain region by a dielectric inner spacer disposed on opposite sides of the first metal gate stack. The second gate-all-around device includes a second metal gate stack surrounding a second channel layer. The second metal gate stack is separated from a second source/drain region by an epitaxial layer disposed on opposite sides of the second metal gate stack.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 6, 2024
    Inventors: Julien Frougier, Sung Dae Suk, Ruilong Xie, Christopher J. Waskiewicz, Veeraraghavan S. Basker
  • STRUCTURE WITH FRONTSIDE AND BACKSIDE DRAMS
    Publication number: 20240188282
    Abstract: A semiconductor structure having a high cell density is provided in which a frontside dynamic access memory (DRAM) is located on a frontside of a semiconductor substrate, and a backside DRAM is located on a backside of the semiconductor substrate. Peripheral transistors can be located on the frontside of the semiconductor substrate and at a same level as frontside transistors of the frontside DRAM.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 6, 2024
    Inventors: Min Gyu Sung, Kangguo Cheng, Ruilong Xie, Chanro Park, Julien Frougier
  • STACKED TRANSISTORS HAVING BOTTOM CONTACT WITH LARGER SILICIDE
    Publication number: 20240186325
    Abstract: A stacked transistor structure including a top source drain region above a bottom source drain region, where a width of the bottom source drain region is greater than a width of the top source drain region, a bottom contact structure directly above and in electrical contact with the bottom source drain region, a metal silicide between the bottom source drain region and the bottom contact structure, the metal silicide having a width larger than a width of the bottom contact structure; a replacement spacer surrounding the bottom contact structure; and a top gate spacer separating the replacement spacer from a gate conductor.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 6, 2024
    Inventors: Koichi Motoyama, Ruilong Xie, Julien Frougier, Nicolas Jean Loubet, Kangguo Cheng
  • VIA AND SOURCE/DRAIN CONTACT LANDING UNDER POWER RAIL
    Publication number: 20240186387
    Abstract: A microelectronic structure including a first nano device that includes a plurality of first transistors and the plurality of first transistors includes at least one first source/drain. A second nano device includes a plurality of second transistors and the second nano device is oriented parallel to the first nano device. The plurality of second transistors includes at least two second source/drains. A gate cut located between the first nano device and the second nano device. A source/drain contact connected to the at least one first source/drain and is connected to at least one of the second source/drains. A portion of the source/drain contact extends parallel to the first nano device and the second nano device.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 6, 2024
    Inventors: Ruilong Xie, Min Gyu Sung, Chanro Park, Kangguo Cheng, Julien Frougier
  • Dual dielectric pillar fork sheet device
    Patent number: 12002808
    Abstract: A forksheet transistor device includes a dual dielectric pillar that includes a first dielectric and a second dielectric that is different from the first dielectric. The dual dielectric pillar physically separates pFET elements from nFET elements. For example, the first dielectric physically separates a pFET gate from a nFET gate while the second dielectric physically separates a pFET source/drain region from a nFET source drain region. When it is advantageous to electrically connect the pFET gate and the nFET gate, the first dielectric may be etched selective to the second dielectric to form a gate connector trench within the dual dielectric pillar. Subsequently, an electrically conductive gate connector strap may be formed within the gate connector trench to electrically connect the pFET gate and the nFET gate.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 4, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Julien Frougier, Kangguo Cheng, Dimitri Houssameddine
  • Nanosheet-based semiconductor structure with dielectric pillar
    Patent number: 12002850
    Abstract: A semiconductor structure includes a substrate, a first device disposed on the substrate and a second device disposed on the substrate. The first device includes a first plurality of nanosheets comprising a p-type material. The second device includes a second plurality of nanosheets comprising an n-type material. A dielectric isolation pillar is disposed between the first device and the second device.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 4, 2024
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Julien Frougier, Ruilong Xie, Chanro Park
  • PHASE CHANGE MEMORY
    Publication number: 20240180047
    Abstract: An apparatus includes a substrate that has an upper face; a first electrode that is attached to the upper face of the substrate; a second electrode that is attached to the upper face of the substrate at a distance from the first electrode; and a bridge of phase-change-memory material that is attached to and lies along the upper face of the substrate between and electrically connecting the first and second electrodes. At least a portion of the bridge is thermally switchable between a low resistance solid phase and a high resistance solid phase. In some embodiments, the apparatus also includes access devices that are disposed between the electrodes and the substrate, with the bridge being electrically connected between the access devices. At least a portion of the bridge is thermally switchable between a low resistance solid phase and a high resistance solid phase.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventors: Kangguo Cheng, Juntao Li, Julien Frougier, Ruilong Xie
  • SUPPORT DIELECTRIC FIN TO PREVENT GATE FLOP-OVER IN NANOSHEET TRANSISTORS
    Publication number: 20240178156
    Abstract: One or more systems, devices, and/or methods of fabrication provided herein relate to nanosheet transistors with support dielectric pillars. According to one embodiment, a transistor device can comprise an active transistor fin and a support dielectric pillar located adjacent to the active transistor fin, wherein the support dielectric pillar stabilizes the active transistor fin.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Juntao Li, Min Gyu Sung, Ruilong Xie, Julien Frougier, Chanro Park
  • THREE DIMENSIONAL RERAM DEVICE
    Publication number: 20240179924
    Abstract: A resistive random access memory (ReRAM) device and a method for forming the device are provided. The ReRAM device includes a first electrode, a resistive switching element layer in contact with the first electrode, and a plurality of second electrodes in contact with the resistive switching element layer. Protruding portions of the first electrode and the resistive switching element layer overlap with the plurality of second electrodes in a vertical direction of the ReRAM device to form a plurality of vertically stacked ReRAM cells.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Inventors: Min Gyu Sung, Soon-Cheon Seo, Heng Wu, Julien Frougier, Chen Zhang, Ruilong Xie
  • LOCAL INTERCONNECT FORMATION AT DOUBLE DIFFUSION BREAK
    Publication number: 20240178136
    Abstract: A microelectronic structure including a first nano device that includes a plurality of first transistors and a second nano device that includes a plurality of second transistors. The first nano device and the second nano device are parallel to each other. A doubled diffusion break that extends across the first nano device and the second nano device. A back-end-of-the-line (BEOL) layer located on a frontside of the first nano device and the second nano device. A backside interconnect located on a backside of the first nano device and the second nano device and the BEOL layer is connected to the backside interconnect through the double diffusion break.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventors: Ruilong Xie, Min Gyu Sung, Julien Frougier, Chanro Park, Kangguo Cheng