Abstract: Disclosed is a technique for switching from a master node to a secondary node in a communication system. A method of a first communication node may comprise: adding the first communication node as a primary secondary cell (PSCell) to a second communication node through dual connectivity (DC); generating a first user plane path for smart dynamic switching (SDS) and a first instance for supporting the first user plane path according to a request from the second communication node; transmitting information on the first user plane path and the first instance to a terminal; receiving user data based on the first user plane path from the terminal as the first instance; and transmitting the user data to a core network using the first user plane path.

Abstract: A display device includes a substrate; a transistor disposed on the substrate; a first insulating layer disposed on the transistor; and a first pixel electrode and a second pixel electrode disposed on the first insulating layer to be adjacent to each other. The first insulating layer includes a first opening between the first pixel electrode and the second pixel electrode.

Abstract: A wireless power transmission/reception system includes a wireless power transmission circuit and a wireless power reception circuit. The wireless power transmission circuit includes an oscillator, a DC-AC converter that converts a direct current to an alternating current and is turned on/off in response to a control signal, a power transmission coil that transmits AC power, a signal reception coil, and a signal receiver that transfers the control signal to the DC-AC converter. The wireless power reception circuit includes a power reception coil, a rectifier that converts an alternating current to a direct current and is turned on or off in response to the control signal, an control signal generator that generates the control signal, a signal transmission coil, and a signal transmitter that transmits the control signal through the signal transmission coil.

Abstract: A memory device may include a plurality of memory cells; one or more backup memory cells; a test circuit suitable for performing a backup operation and a test operation to a test target cell selected among the plurality of memory cells; and a control circuit suitable for accessing the backup memory cells instead of the test target cell during the performance of the test operation after completion of the backup operation for the selected test target cell, wherein, during the backup operation, the test circuit controls the control circuit to copy an original data of the test target cell to a corresponding backup memory cell selected among the backup memory cells, and wherein, during the test operation, the test circuit determines whether the test target cell is a pass or a fail.

Abstract: A memory device may include: a plurality of memory cells; at least one address storage unit; a fail detection unit suitable for comparing first and second read data that are read from at least one memory cell selected among the plurality of memory cells to detect a fail, and storing an address of the selected memory cell in the address storage unit when the fail is detected; and a refresh control unit suitable for refreshing the memory cell corresponding to the address stored in the address storage unit at a higher frequency than the other memory cells.

Abstract: A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.

Abstract: A reconfigurable semiconductor memory apparatus may include a memory cell array including a plurality of sub arrays. The reconfigurable semiconductor memory apparatus may include an information storage unit configured to store status information for each sub array, and a reset address according to the status information.

Abstract: A memory device may include a plurality of memory cells; one or more backup memory cells; a test circuit suitable for performing a backup operation and a test operation to a test target cell selected among the plurality of memory cells; and a control circuit suitable for accessing the backup memory cells instead of the test target cell during the performance of the test operation after completion of the backup operation for the selected test target cell, wherein, during the backup operation, the test circuit controls the control circuit to copy an original data of the test target cell to a corresponding backup memory cell selected among the backup memory cells, and wherein, during the test operation, the test circuit determines whether the test target cell is a as a pass or a fail.

Abstract: A memory device includes a plurality of memory cells; a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and sequentially transmitting the sensed weak addresses; a weak address control block suitable for latching the weak addresses transmitted from the nonvolatile memory block, and outputting sequentially the latched weak addresses in a weak refresh operation; and a refresh control block suitable for controlling the memory cells corresponding to the counting address to be refreshed, in a normal refresh operation, and controlling the memory cells corresponding to the weak address to be refreshed, in the weak refresh operation.

Abstract: A refresh control device is disclosed, which relates to a technology for efficiently storing weak cell refresh addresses. The refresh control device includes a weak cell address storage circuit to store a weak address, a weak cell address control circuit, and a row address control circuit. The weak cell address control circuit outputs a weak enable signal and a row address by comparing a refresh address with the weak address, and only activates the refresh address according to the comparison result or activates both the refresh address and the row address. The row address control circuit controls a refresh operation by selectively activating a word line of a bank in response to the refresh address, the weak enable signal, and the row address.

Abstract: A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.

Abstract: A semiconductor device may include: a first latch configured to store data outputted from a memory cell during a first operation; and a fail detection circuit configured to detect a fail by comparing the data outputted from the memory cell to the data stored in the first latch through a second operation performed at a predetermined time after the first operation.

Abstract: A memory apparatus includes a first memory bank, a second memory bank, a row decoder and repair circuit, and an input/output driver controller. The row decoder and repair circuit is coupled to the first and second memory banks in common. The row decoder and repair circuit generates a shared repair signal according to whether a word line disposed in a first memory bank is replaced with a word line disposed in a second memory bank. The input/output driver controller allows read or write operations for one of the first and second memory banks to be performed based on the shared repair signal and an operation signal.

Abstract: A memory device may include: a plurality of memory cells; at least one address storage unit; a fail detection unit suitable for comparing first and second read data that are read from at least one memory cell selected among the plurality of memory cells to detect a fail, and storing an address of the selected memory cell in the address storage unit when the fail is detected; and a refresh control unit suitable for refreshing the memory cell corresponding to the address stored in the address storage unit at a higher frequency than the other memory cells.

Abstract: A wireless power transmission/reception system includes a wireless power transmission circuit and a wireless power reception circuit. The wireless power transmission circuit includes an oscillator, a DC-AC converter that converts a direct current to an alternating current and is turned on/off in response to a control signal, a power transmission coil that transmits AC power, a signal reception coil, and a signal receiver that transfers the control signal to the DC-AC converter. The wireless power reception circuit includes a power reception coil, a rectifier that converts an alternating current to a direct current and is turned on or off in response to the control signal, an control signal generator that generates the control signal, a signal transmission coil, and a signal transmitter that transmits the control signal through the signal transmission coil.

Abstract: A semiconductor device may include: a first latch configured to store data outputted from a memory cell during a first operation; and a fail detection circuit configured to detect a fail by comparing the data outputted from the memory cell to the data stored in the first latch through a second operation performed at a predetermined time after the first operation.

Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals.

Abstract: A wireless power transmission/reception system includes a wireless power transmission circuit and a wireless power reception circuit. The wireless power transmission circuit includes an oscillator, a DC-AC converter that converts a direct current to an alternating current and is turned on/off in response to a control signal, a power transmission coil that transmits AC power, a signal reception coil, and a signal receiver that transfers the control signal to the DC-AC converter. The wireless power reception circuit includes a power reception coil, a rectifier that converts an alternating current to a direct current and is turned on or off in response to the control signal, an control signal generator that generates the control signal, a signal transmission coil, and a signal transmitter that transmits the control signal through the signal transmission coil.

Abstract: A reconfigurable semiconductor memory apparatus may include a memory cell array including a plurality of sub arrays. The reconfigurable semiconductor memory apparatus may include an information storage unit configured to store status information for each sub array, and a reset address according to the status information.

Abstract: A system for repairing a plurality of semiconductor chips each comprising a data storage region including electric fuses connected to the data storage regions of the plurality of semiconductor chips, a defect determination unit configured to read the data of a chip that is actually accessed and the data of an idle chip in the data storage regions, compare the actually accessed and read data with the data of the idle chip, and detect a defect based on a result of the comparison, a storage unit configured to store the defective position of the defect according to a result of the defect determination unit, and a repair unit configured to repair the defect through an E fuse connected to the position of the defect using a reset signal.