Abstract: A digital temperature sensing device uses temperature depending characteristic of contact resistance of a MOS transistor and a self-refresh driving device adjusts its self-refresh period depending on temperature using the digital temperature sensing device. The self-refresh driving device includes a first reference voltage generating unit for generating a reference voltage robust to temperature, the first reference voltage generating means being formed with a plurality of MOS transistors, the number of source contacts of the MOS transistors being adjusted such that variation of saturation current through source-drain is compensated for; a second reference voltage generating unit for generating a second reference voltage sensitive to temperature; a level comparator for comparing the first reference voltage with the second reference voltage; and an oscillator for generating a clock signals having differing period depending on the output signal of the level comparator.

Abstract: A core voltage discharge driver prevents a core voltage discharging operation from interrupting the core voltage generating operation. The core voltage discharge driver includes a comparing unit configured to compare a core voltage generating control signal for controlling generation of a core voltage with a core voltage discharging control signal for controlling discharge of the core voltage, and an adjusting unit configured to adjust the core voltage discharging control signal based on a comparison result of the comparing unit.

Abstract: A data output driver device includes a noise detecting unit configured to output a noise detection signal to detect variations of power supply voltage due to noise, and a driver circuit unit configured to drive and output data with the variable driving capability in response to the noise detection signal.

Abstract: An internal voltage generator for use in a semiconductor memory device includes a first voltage detection unit, a second voltage detection unit, a detection signal generation unit, and an internal voltage generation unit. The first voltage detection unit detects a voltage level of an internal voltage changing linearly depending on a temperature variation to output a first detection signal. The second voltage detection unit detects the voltage level having a constant value without concerning the temperature variation to output a second detection signal. The detection signal output unit combines the first and the second detection signal to generate a combined detection signal for detecting the voltage level linearly varying according to the temperature variation in a first range of temperature and detecting the voltage level having the constant value in a second range of temperature.

Abstract: The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a sense amplifier includes a sense amplifying circuit sensing and amplifying data loaded on a bit line with a first power. A power supplying unit provides the first power to the sense amplifying circuit. A decoupling unit generates a decoupling noise with a second power and provides the decoupling noise to the first power voltage. The decoupling noise is maintained for a period including a time point of an operation of the sense amplifying circuit and a predetermined time thereafter.

Abstract: A voltage control apparatus and a method of controlling a voltage using the same. A voltage control apparatus includes a signal generator configured to output a burn-in control signal and a burn-in precharge signal in response to an all bank precharge command, and a voltage controller configured to supply either a first voltage or a second voltage lower than the first voltage to a word line in response to the burn-in control signal and the burn-in precharge signal.

Abstract: An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a predetermined frequency. The operation clock controller includes a clock buffer for buffering an external clock to output an internal clock; a unit delaying set for sequentially delaying the internal clock to output a plurality of delayed clocks; a phase detecting block for detecting logic levels of the delayed clocks at a rising edge of the internal clock to output phase detecting signals; a sampling pulse generator for outputting a sampling signal generated at a predetermined point of the internal clock; a latching block for outputting a phase detection latch signal by sampling and latching the phase detection signal at a point of the sampling signal being inputted; and a frequency detection block for outputting the frequency detection signal by logically combining the phase detection latch signal.

Abstract: A core voltage discharge driver prevents a core voltage discharging operation from interrupting the core voltage generating operation. The core voltage discharge driver includes a comparing unit configured to compare a core voltage generating control signal for controlling generation of a core voltage with a core voltage discharging control signal for controlling discharge of the core voltage, and an adjusting unit configured to adjust the core voltage discharging control signal based on a comparison result of the comparing unit.

Abstract: A voltage control apparatus and a method of controlling a voltage using the same. A voltage control apparatus includes a signal generator configured to output a burn-in control signal and a burn-in precharge signal in response to an all bank precharge command, and a voltage controller configured to supply either a first voltage or a second voltage lower than the first voltage to a word line in response to the burn-in control signal and the burn-in precharge signal.

Abstract: A delay detecting apparatus detects delay amounts of delay elements in a semiconductor device by using a test mode. The semiconductor device comprises a delay signal detecting unit for detecting delays of delay elements in the semiconductor device by using a signal that is synchronized with an external clock, and a delay signal outputting unit for outputting a delayed signal from the delay signal detecting unit to a data pad by using the signal that is synchronized with the external clock.

Abstract: An internal voltage generating circuit detects a level of a back bias voltage or a pumping voltage and controls a period of an oscillating signal based on the result of counting timing when the detected voltage is lower than a reference voltage. The internal voltage generating circuit includes a back bias/pumping voltage detector for detecting a level difference between a back bias/pumping voltage and a reference voltage, a period controller for controlling a period of an oscillating signal based on the detection result of the back bias/pumping voltage detector, and a pumping unit for pumping the back bias/pumping voltage according to an activation period of the oscillating signal.

Abstract: A semiconductor device including a threshold voltage detector and a boosted voltage generating unit. The threshold voltage detector detects a threshold voltage level of cell transistors and outputs a detected threshold voltage level. The boosted voltage generating unit changes a target level of a boosted voltage in response to the detected threshold voltage level. The threshold voltage detector includes a detected current generating unit and a detected voltage generating unit. The detected current generating unit has a plurality of cell transistors in a cell array and generates a detected current whose amplitude varies corresponding to an average level of the threshold voltages of the cell transistors. The detected voltage generating unit generates the detected threshold voltage level whose level is determined corresponding to the amplitude of the detected current.

Abstract: An internal voltage generation circuit for a semiconductor device and method therefor includes a voltage generator configured to generate voltages with different levels by using an external voltage. A code storing unit is configured to store a selection code to select an internal voltage out of the plurality of voltages. A decoding unit selects the internal voltage from among the plurality of voltages in response to the selection code in a normal mode, and selects the internal voltage out of the plurality of voltages in response to a test selection code set in a test mode. The interval voltage selected in the normal mode is used as an initial value that is a reference of the selection in the test mode.

Abstract: A semiconductor memory device is capable of generating a back bias voltage based on a target level changed according to a leakage current of the semiconductor memory devices, thereby minimizing the amount of the leakage current. The semiconductor memory device includes a leakage current detector and a back bias voltage generator. The leakage current detector is configured to detect a leakage current of a cell array. The back bias voltage generator is configured to generate a back bias voltage having a target level changed according to the leakage current.

Abstract: An internal voltage generator supplies a stable internal voltage without increasing standby current. The internal voltage generator includes an internal voltage driver for supplying an internal voltage based on a control signal, a feedback circuit for supplying a feedback voltage having a voltage level proportional to the internal voltage, a control signal generating circuit for generating the control signal to control the internal voltage driver such that the feedback voltage is maintained at a desired reference voltage, an auxiliary driving circuit for additionally supplying the internal voltage in response to the control signal, and an auxiliary driving control circuit for activating the auxiliary driving circuit only when it is expected to dissipate a large amount of a current.

Abstract: A circuit and method for easily detecting skew of a transistor within a semiconductor device are provided. The circuit for detecting the skew of the transistor includes a linear voltage generating unit for outputting a linear voltage by using a first supply voltage, a first attenuation unit for reducing variation width of the linear voltage according to the performance of the transistor, a saturation voltage generating unit for outputting a saturation voltage by using a second supply voltage, and a comparison unit for comparing an output of the first attenuation unit and the saturation voltage.

Abstract: The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying a first power voltage; a second power voltage supply line for supplying a second power voltage; a first reservoir capacitor for supplying the first and the second power voltages stably; and a reservoir capacitor controller for selectively connecting the first reservoir capacitor to the first power voltage supply line or the second power voltage supply line.

Abstract: A voltage control apparatus and a method of controlling a voltage using the same. A voltage control apparatus includes a signal generator configured to output a burn-in control signal and a burn-in precharge signal in response to an all bank precharge command, and a voltage controller configured to supply either a first voltage or a second voltage lower than the first voltage to a word line in response to the burn-in control signal and the burn-in precharge signal.

Abstract: An internal voltage generator of a semiconductor memory device controls generating an internal voltage according to an increase of the internal voltage during an active mode, to thereby decrease current consumption. The internal voltage generator of a semiconductor memory device includes a voltage sensor, a plurality of first control units, a plurality of second control units, and a plurality of voltage drivers. The voltage sensor detects an internal voltage. The plurality of first control units generate a plurality of internal control signals according to the voltage level of an output of the voltage sensor. The plurality of second control units generate a plurality of driver control signals in response to the plurality of internal control signals. The plurality of voltage drivers are turned on/off in response to the plurality of driver control signals.

Abstract: The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying a first power voltage; a second power voltage supply line for supplying a second power voltage; a first reservoir capacitor for supplying the first and the second power voltages stably; and a reservoir capacitor controller for selectively connecting the first reservoir capacitor to the first power voltage supply line or the second power voltage supply line.