Abstract: A voltage supply apparatus includes a power noise sensing unit, a voltage selecting unit, a first power voltage supply unit and a second power voltage supply unit. The power noise sensing unit senses noise from first and second powers and outputs a power noise sensing signal. The voltage selecting unit outputs first and second driving signals in response to a voltage-supply-enable-signal and the power noise sensing signal. The first power voltage supply unit applies a voltage of the first power in response to the first and second driving signals. The second power voltage supply unit applies a voltage of the second power in response to the first and second driving signals.

Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals.

Abstract: A fuse circuit includes an electric fuse coupled to a first voltage source; a low resistance unit coupled to the electric fuse and having a junction which is capable of breaking down; and a switching unit coupled between the low resistance unit and a second voltage source.

Abstract: A voltage supply apparatus includes a power noise sensing unit, a voltage selecting unit, a first power voltage supply unit and a second power voltage supply unit. The power noise sensing unit senses noise from first and second powers and outputs a power noise sensing signal. The voltage selecting unit outputs first and second driving signals in response to a voltage-supply-enable-signal and the power noise sensing signal. The first power voltage supply unit applies a voltage of the first power in response to the first and second driving signals. The second power voltage supply unit applies a voltage of the second power in response to the first and second driving signals.

Abstract: Provided is a semiconductor integrated circuit. The semiconductor integrated circuit comprises: a pair of interconnections; a fuse connecting the pair of interconnections; and one or more heat dissipation patterns connecting the pair of interconnections and are disposed around the fuse.

Abstract: A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.

Abstract: A voltage control apparatus and a method of controlling a voltage using the same. A voltage control apparatus includes a signal generator configured to output a burn-in control signal and a burn-in precharge signal in response to an all bank precharge command, and a voltage controller configured to supply either a first voltage or a second voltage lower than the first voltage to a word line in response to the burn-in control signal and the burn-in precharge signal.

Abstract: A circuit and method for generating a word line off voltage which can minimize a leakage current by actively adjusting a level of the word line off voltage. The circuit includes a current information provider for providing information about an amount of current flowing through a cell transistor, and a voltage generator for generating a word line off voltage with a varying level depending on the information.

Abstract: A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line.

Abstract: The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a sense amplifier includes a sense amplifying circuit sensing and amplifying data loaded on a bit line with a first power. A power supplying unit provides the first power to the sense amplifying circuit. A decoupling unit generates a decoupling noise with a second power and provides the decoupling noise to the first power voltage. The decoupling noise is maintained for a period including a time point of an operation of the sense amplifying circuit and a predetermined time thereafter.

Abstract: A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.

Abstract: A semiconductor memory device is capable of generating a back bias voltage based on a target level changed according to a leakage current of the semiconductor memory devices, thereby minimizing the amount of the leakage current. The semiconductor memory device includes a leakage current detector and a back bias voltage generator. The leakage current detector is configured to detect a leakage current of a cell array. The back bias voltage generator is configured to generate a back bias voltage having a target level changed according to the leakage current.

Abstract: A semiconductor package capable of being efficiently stacked and a method of manufacturing the same is presented. The semiconductor package includes a semiconductor chip, an insulation layer, and a through-electrode. The semiconductor chip has a first surface and a second surface, a circuit section in the semiconductor chip, an internal circuit pattern electrically connected to the circuit section, and a through-hole that passes through the internal circuit pattern and through the first and second surfaces. The insulation layer is on a through-hole of the semiconductor chip and has an opening which exposes the internal circuit pattern which was exposed by the through-hole. The through-electrode is in the through-hole and electrically coupled to the internal circuit pattern which is exposed through the opening of the insulation layer.

Abstract: The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a sense amplifier includes a sense amplifying circuit sensing and amplifying data loaded on a bit line with a first power. A power supplying unit provides the first power to the sense amplifying circuit. A decoupling unit generates a decoupling noise with a second power and provides the decoupling noise to the first power voltage. The decoupling noise is maintained for a period including a time point of an operation of the sense amplifying circuit and a predetermined time thereafter.

Abstract: An internal voltage generation circuit for a semiconductor device and method therefor includes a voltage generator configured to generate voltages with different levels by using an external voltage. A code storing unit is configured to store a selection code to select an internal voltage out of the plurality of voltages. A decoding unit selects the internal voltage from among the plurality of voltages in response to the selection code in a normal mode, and selects the internal voltage out of the plurality of voltages in response to a test selection code set in a test mode. The interval voltage selected in the normal mode is used as an initial value that is a reference of the selection in the test mode.

Abstract: A semiconductor device including a threshold voltage detector and a boosted voltage generating unit. The threshold voltage detector detects a threshold voltage level of cell transistors and outputs a detected threshold voltage level. The boosted voltage generating unit changes a target level of a boosted voltage in response to the detected threshold voltage level. The threshold voltage detector includes a detected current generating unit and a detected voltage generating unit. The detected current generating unit has a plurality of cell transistors in a cell array and generates a detected current whose amplitude varies corresponding to an average level of the threshold voltages of the cell transistors. The detected voltage generating unit generates the detected threshold voltage level whose level is determined corresponding to the amplitude of the detected current.

Abstract: The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying a first power voltage; a second power voltage supply line for supplying a second power voltage; a first reservoir capacitor for supplying the first and the second power voltages stably; and a reservoir capacitor controller for selectively connecting the first reservoir capacitor to the first power voltage supply line or the second power voltage supply line.

Abstract: A circuit and method for generating a word line off voltage which can minimize a leakage current by actively adjusting a level of the word line off voltage. The circuit includes a current information provider for providing information about an amount of current flowing through a cell transistor, and a voltage generator for generating a word line off voltage with a varying level depending on the information.

Abstract: A circuit and method for easily detecting skew of a transistor within a semiconductor device are provided. The circuit for detecting the skew of the transistor includes a linear voltage generating unit for outputting a linear voltage by using a first supply voltage, a first attenuation unit for reducing variation width of the linear voltage according to the performance of the transistor, a saturation voltage generating unit for outputting a saturation voltage by using a second supply voltage, and a comparison unit for comparing an output of the first attenuation unit and the saturation voltage.

Abstract: An internal voltage generator of a semiconductor memory device controls generating an internal voltage according to an increase of the internal voltage during an active mode, to thereby decrease current consumption. The internal voltage generator of a semiconductor memory device includes a voltage sensor, a plurality of first control units, a plurality of second control units, and a plurality of voltage drivers. The voltage sensor detects an internal voltage. The plurality of first control units generate a plurality of internal control signals according to the voltage level of an output of the voltage sensor. The plurality of second control units generate a plurality of driver control signals in response to the plurality of internal control signals. The plurality of voltage drivers are turned on/off in response to the plurality of driver control signals.