Abstract: An eyewear device has an antenna system having at least one element which contributes to wireless signal transmission, and which is thermally connected to a heat-generating electronic component of the eyewear device to serve as a heat sink for the electronic component. A driven antenna element and/or a plurality of PCB extenders electrically connected to a PCB ground plane can thus be employed for both signal transmission and heat management.

Abstract: A hinge assembly mounted on a housing of form part of an electronic device includes a metal hinge member having a hinge post that extends through a mounting hole in a wall of the housing, the hinge post being connected to a metal anchor plate on an inner side of the housing wall to be rotationally and axially fast with the anchor plate. The anchor plate may has an area multiple times the size of a footprint of the hinge member, with fastening the hinge post and the anchor plate in some embodiments being by a welded connection.

Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.

Abstract: The present disclosure discloses a seismic vibrator, a vibration device and a driving apparatus for the same. The seismic vibrator comprises: a base; a mounting plate; a first spring configured to connect the base and the mounting plate, so that the mounting plate reciprocates relative to the base; a coil fixed with the base; a magnet having one end fixed with the mounting plate, and the other end stretched into the coil; a magnetic steel fixed with the magnet, wherein a gap for accommodating the coil is provided between the magnetic steel and the magnet; and a counterweight fixed with the mounting plate. The vibration device comprises the above seismic vibrator and an adjustable base. Compared with the traditional electromagnetic controllable seismic vibrator, the structure of the seismic vibrator provided by the present disclosure is simpler.

Abstract: Provided is a graphene-based aqueous coating suspension comprising multiple graphene sheets, particles of an anti-corrosive pigment or sacrificial metal, and a waterborne binder resin dissolved or dispersed in water, wherein the multiple graphene sheets contain single-layer or few-layer graphene sheets selected from a pristine graphene material having essentially zero % of non-carbon elements, or a non-pristine graphene material having 0.001% to 47% by weight of non-carbon elements wherein the non-pristine graphene is selected from graphene oxide, reduced graphene oxide, graphene fluoride, graphene chloride, graphene bromide, graphene iodide, hydrogenated graphene, nitrogenated graphene, doped graphene, chemically functionalized graphene, or a combination thereof and wherein the coating suspension does not contain a silicate binder or microspheres dispersed therein. Also provided is an object or structure coated at least in part with such a coating.

Abstract: A memory device including a memory cell array, a redundant fuse circuit and a memory controller is provided. The memory cell array includes multiple regular memory blocks and multiple redundant memory blocks. The redundant fuse circuit includes multiple fuse groups recording multiple repair information. Each repair information is associated with a corresponding one of the redundant memory blocks and includes a repair address, a first enable bit, and a second enable bit. The memory controller includes multiple determining circuits. Each of the multiple determining circuits generates a hit signal according to an operation address, the repair address, the first enable bit, and the second enable bit. When a target memory block is bad, and the determining circuit of the memory controller generates the hit signal, the memory controller disables the redundant memory block that is bad according to the hit signal.

Abstract: The disclosure provides an audio processing device comprising a first filter and a second filter. The first filter is configured to generate a first filtered signal based on an error signal, the error signal representative of audible sound at a target space. The second filter is configured to generate a second filtered signal based on the error signal. An anti-noise signal is generated based on the first filtered signal and the second filtered signal, and the anti-noise signal is included in the error signal. The first filter is connected to the second filter in parallel.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

Abstract: A carry case for an electronics-enabled eyewear device, such as smart glasses, has charging contacts that are movable relative to a storage chamber in which the eyewear device is receivable. The charging contacts are connected to a battery carried by the case for charging the eyewear device via contact coupling of the charging contacts to corresponding contact formations on an exterior of the eyewear device. The charging contacts are in some instances mounted on respective flexible walls defining opposite extremities of the storage chamber. The contact formations on the eyewear device are in some instances provided by hinge assemblies that couple respective temples to a frame of the eyewear device.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a first inter-metal dielectric (IMD) layer on the MTJ, removing part of the first IMD layer to form a damaged layer on the MTJ and a trench exposing the damaged layer, performing a ultraviolet (UV) curing process on the damaged layer, and then conducting a planarizing process to remove the damaged layer and part of the first IMD layer.

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed on the gate.

Abstract: A light sensing module and an electronic device using the same are provided. The light sensing module includes a substrate, a light sensing unit, a first light-transmissive component and a blocking wall. The light sensing unit is disposed on the substrate to sense an intensity of a working light beam. The first light-transmissive component covers the light sensing unit, and has a first refractive index that is between a refractive index of the light sensing unit and a refractive index of air. The blocking wall is disposed on the substrate, and surrounds the light sensing unit and the first light-transmissive component.

Abstract: A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.

Abstract: A multi-button lamp power supply or controller, comprising a shell and a circuit board arranged in the shell, and further comprising: a first mode switching component, wherein one end of the first mode switching component fits with the shell, and the other end of the first mode switching component is positioned inside the shell and fits with the circuit board; and a second mode switching component, wherein one end of the second mode switching component fits with the shell, and the other end of the second mode switching component is positioned inside the shell and fits with the circuit board. The utility model has the advantages of simple operation.

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

Abstract: Provided is a metal matrix nanocomposite comprising: (a) a metal or metal alloy as a matrix material; and (b) multiple graphene sheets that are dispersed in said matrix material, wherein said multiple graphene sheets are substantially aligned to be parallel to one another and are in an amount from 0.1% to 95% by volume based on the total nanocomposite volume; wherein the multiple graphene sheets contain single-layer or few-layer graphene sheets selected from pristine graphene, graphene oxide, reduced graphene oxide, graphene fluoride, graphene chloride, graphene bromide, graphene iodide, hydrogenated graphene, nitrogenated graphene, doped graphene, chemically functionalized graphene, or a combination thereof and wherein the chemically functionalized graphene is not graphene oxide. The metal matrix exhibits a combination of exceptional tensile strength, modulus, thermal conductivity, and/or electrical conductivity.

Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile stress pieces.

Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.