Patents by Inventor Jun Lin

Jun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947390
    Abstract: A case for an eyewear device includes a body defining an opening leading to a storage chamber that is sized for retaining the eyewear device. A cover depends from the body and is movable between an open position, in which the opening is exposed, and a closed position, in which the opening is covered by the cover. A battery is mounted to the body for charging the eyewear device. A detector is positioned on either the body or the cover for detecting when the cover is in the open position or the closed position. A display displays a charge state of the battery when the cover is in the open position.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 2, 2024
    Assignee: Snap Inc.
    Inventors: John Bernard Ardisana, II, Emily Lauren Clopp, Teodor Dabov, Mathias Hintermann, Jinwoo Kim, Jun Lin, Ashutosh Y. Shukla
  • Patent number: 11945971
    Abstract: Provided is a graphene-based coating suspension comprising multiple graphene sheets, thin film coating of an anti-corrosive pigment or sacrificial metal deposited on graphene sheets, and a binder resin dissolved or dispersed in a liquid medium, wherein the multiple graphene sheets contain single-layer or few-layer graphene sheets selected from a pristine graphene material having essentially zero % of non-carbon elements, or a non-pristine graphene material having 0.001% to 47% by weight of non-carbon elements wherein the non-pristine graphene is selected from graphene oxide, reduced graphene oxide, graphene fluoride, graphene chloride, graphene bromide, graphene iodide, hydrogenated graphene, nitrogenated graphene, doped graphene, chemically functionalized graphene, or a combination thereof. The invention also provides a process for producing this coating suspension. Also provided is an object or structure coated at least in part with such a coating.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: April 2, 2024
    Assignee: Global Graphene Group, Inc.
    Inventors: Fan-Chun Meng, Yi-jun Lin, Shaio-yen Lee, Wen Y. Chiu, Aruna Zhamu, Bor Z. Jang
  • Patent number: 11946704
    Abstract: Provided is a elastic heat spreader film comprising: (a) an elastomer or rubber as a binder material or a matrix material; and (b) multiple graphene sheets that are bonded by the binder material or dispersed in the matrix material, wherein the multiple graphene sheets are substantially aligned to be parallel to one another and wherein the elastomer or rubber is in an amount from 0.001% to 20% by weight based on the total heat spreader film weight; wherein the multiple graphene sheets contain single-layer or few-layer graphene sheets selected from pristine graphene, graphene oxide, reduced graphene oxide, graphene fluoride, graphene chloride, graphene bromide, graphene iodide, hydrogenated graphene, nitrogenated graphene, doped graphene, chemically functionalized graphene, or a combination thereof; and wherein the elastic heat spreader film has a fully recoverable tensile elastic strain from 2% to 100% and an in-plane thermal conductivity from 200 W/mK to 1,750 W/mK.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 2, 2024
    Assignee: Global Graphene Group, Inc.
    Inventors: Yi-jun Lin, Bor Z. Jang
  • Patent number: 11942150
    Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Zheng-Jun Lin, Pei-Ling Tseng
  • Publication number: 20240081500
    Abstract: A carry case for an electronics-enabled eyewear device, such as smart glasses, has charging contacts that are movable relative to a storage chamber in which the eyewear device is receivable. The charging contacts are connected to a battery carried by the case for charging the eyewear device via contact coupling of the charging contacts to corresponding contact formations on an exterior of the eyewear device. The charging contacts are in some instances mounted on respective flexible walls defining opposite extremities of the storage chamber. The contact formations on the eyewear device are in some instances provided by hinge assemblies that couple respective temples to a frame of the eyewear device.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Jinwoo Kim, Jun Lin
  • Publication number: 20240079451
    Abstract: A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and first and second dielectric walls. The substrate includes first and second fins. The first and second stacks of semiconductor nanosheets are disposed on the first and second fins respectively. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first and second strained layers are respectively disposed on the first and second fins and abutting the first and second stacks of semiconductor nanosheets. The first dielectric wall is disposed on the substrate and located between the first and second strained layers. The second dielectric wall is disposed on the first dielectric wall and located between the first and second strained layers. A top surface of the second dielectric wall is lower than top surfaces of the first and second strained layers.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun Lin, Tzu-Hung Liu, Chun-Jun LIN, Chih-Hao Chang, Jhon Jhy Liaw
  • Publication number: 20240081154
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai, Da-Jun Lin, Chau-Chung Hou, Wei-Xin Gao
  • Patent number: 11921357
    Abstract: Apparatuses, systems for electronic wearable devices such as smart glasses are described. The wearable device can comprise a frame, an elongate temple and an articulated joint. The frame can define one or more optical element holders configured to hold respective optical elements for viewing by a user in a viewing direction. The temple can be moveably connected to the frame for holding the frame in position when the device is worn by the user. The articulated joint can connect the temple and the frame to permit movement of the temple relative to the frame between a wearable position in which the temple is generally aligned with the viewing direction, and a collapsed position in which the temple extends generally transversely to the viewing direction. The articulated joint can include abase foot fixed to the frame and oriented transversely to the viewing direction.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: March 5, 2024
    Assignee: Snap Inc.
    Inventors: Nicholas Streets, Jun Lin, Stephen Steger
  • Publication number: 20240062815
    Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 22, 2024
    Inventors: Zheng-Jun LIN, Chung-Cheng CHOU, Pei-Ling TSENG
  • Publication number: 20240063294
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a plurality of dummy gates over a substrate and performing a first etch step and a second etch step on the substrate exposed between the dummy gates. The first etch step includes an anisotropic etching process and an isotropic etching process. The second includes an isotropic etching step.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventors: Ta-Chun LIN, Jyun-Yang SHEN, Hsiang-Yu LAI, Shih-Chang TSAI, Chun-Jun LIN, Kuo-Hua PAN, Jhon Jhy LIAW
  • Patent number: 11910506
    Abstract: The present disclosure discloses A lamp controller, comprising a DC power supply and a switch unit, wherein an output end of the DC power supply is electrically connected to the switch unit, the switch unit comprises a first switch set, a second switch set and a control module for controlling the first switch set and the second switch set to be turned on alternately, an output end of the control module is electrically connected to the first switch set, and the output end of the control module forms a second set of switch circuit after being electrically connected to the second switch set; and the lamp controller further comprises a control unit, which is electrically connected to the switch unit; the switch unit further comprises: a first toggle switch.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: February 20, 2024
    Assignee: Changzhou Jutai Electronic Co., Ltd.
    Inventors: Jun Lin, Chengqian Pan, Wei Huang, Jin Chen
  • Publication number: 20240055935
    Abstract: A motor shaft anti-rotation structure which is applied to secure a motor shaft to a carrier includes an anti-rotation sleeve and a screwing member. The anti-rotation sleeve includes a sleeve wall surrounding and defining an inner space, a pressing portion protruding radially and inward from the sleeve wall to separate the inner space into a motor shaft region and a screwing member region, a through hole penetrating the pressing portion and communicated with the motor shaft region and the screwing member region, and a restricting protrusion protruding outward from the sleeve wall and corresponding to an inserted hole of the carrier. The screwing member includes a threaded portion inserting in the through hole to screw into the motor shaft, and a head portion connected to the threaded portion and configured to press against the pressing portion. The head portion is configured to be received in the screwing member region.
    Type: Application
    Filed: December 22, 2022
    Publication date: February 15, 2024
    Inventor: En-Jun LIN
  • Publication number: 20240047561
    Abstract: A method includes forming a semiconductor fin over a substrate; forming isolation structures laterally surrounding the semiconductor fin; forming a gate structure over the semiconductor fin; forming a first spacer layer and a second spacer layer over the gate structure and the semiconductor fin; etching back the second spacer layer, such that a top surface of the second spacer layer is lower than a top surface of the first spacer layer; after etching back the second spacer layer, forming a third spacer layer over the first spacer layer and the second spacer layer; etching the first, second, and third spacer layers and the semiconductor fin to form recesses; and forming epitaxial source/drain structures in the recesses.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Ming-Che CHEN, Chun-Jun LIN, Kuo-Hua PAN, Jhon Jhy LIAW
  • Publication number: 20240036597
    Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Chin-I Su
  • Publication number: 20240032433
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a top electrode on the MTJ, a trapping layer in the top electrode for trapping hydrogen, a first inter-metal dielectric (IMD) layer on the MTJ, and a first metal interconnection in the first IMD layer and on the top electrode. Preferably, a top surface of the trapping layer is lower than a bottom surface of the first IMD layer.
    Type: Application
    Filed: October 4, 2023
    Publication date: January 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Tai-Cheng Hou, Bin-Siang Tsai, Ting-An Chien
  • Publication number: 20240023218
    Abstract: The present disclosure discloses A lamp controller, comprising a DC power supply and a switch unit, wherein an output end of the DC power supply is electrically connected to the switch unit, the switch unit comprises a first switch set, a second switch set and a control module for controlling the first switch set and the second switch set to be turned on alternately, an output end of the control module is electrically connected to the first switch set, and the output end of the control module forms a second set of switch circuit after being electrically connected to the second switch set; and the lamp controller further comprises a control unit, which is electrically connected to the switch unit; the switch unit further comprises: a first toggle switch.
    Type: Application
    Filed: September 12, 2022
    Publication date: January 18, 2024
    Inventors: Jun LIN, Chengqian PAN, Wei HUANG, Jin CHEN
  • Publication number: 20240021685
    Abstract: Structures and methods for the co-optimization of various device types include performing a first photolithography and etch process to simultaneously form a first source/drain recess for a first device in a first substrate region and a third source/drain recess for a third device in a third substrate region different than the first substrate region. In some embodiments, the method further includes performing a second photolithography and etch process to form a second source/drain recess for a second device in a second substrate region different than the first and third substrate regions. The method further includes forming a first source/drain feature within the first source/drain recess, a second source/drain feature within the second source/drain recess, and a third source/drain feature within the third source/drain recess.
    Type: Application
    Filed: July 15, 2022
    Publication date: January 18, 2024
    Inventors: Ta-Chun LIN, Jyun-Yang SHEN, Chun-Jun LIN, Kuo-Hua PAN, Jhon Jhy LIAW
  • Publication number: 20240019113
    Abstract: The disclosure discloses A lamp power adapter, comprising an input conductive component, a shell, a circuit board an end cover and a connecting base for connecting load; one end of the input conductive component is located in the shell, the input conductive componentis integrally fixed with the shell, the other end of the input conductive component is exposed outside the shell, an input connecting terminal, a control circuit and an output connecting terminal are arranged on the circuit board, at least a part of the circuit board is located in the shell, the input connecting terminalis electrically connected to one end of the input conductive component, the connecting base is arranged on the end cover, an output conductive component is arranged on the connecting base, when the end cover fits with the shell, the output conductive component is in plugging fit with the output connecting terminal
    Type: Application
    Filed: September 12, 2022
    Publication date: January 18, 2024
    Inventors: Jun LIN, Chengqian PAN, Wei HUANG, Jin CHEN
  • Publication number: 20240014069
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai
  • Publication number: 20240014074
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming first and second semiconductor fins; forming first and second gate structures respectively over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming a n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess.
    Type: Application
    Filed: July 7, 2022
    Publication date: January 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Ming-Che CHEN, Jyun-Yang SHEN, Yu-Chang LIANG, Chun-Jun LIN, Kuo-Hua PAN, Jhon Jhy LIAW