Abstract: The invention provides compositions useful in post-CMP cleaning operations, particularly those substrates which contain exposed copper surfaces. The compositions of the invention provide excellent cleaning of such substrates while showing fewer defects from silica and organic materials present at the surface of the substrate. Also provided is a method for cleaning a microelectronic device substrate using such compositions and a kit comprising, in two or more containers, the components of the compositions.

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

Abstract: A model selection method for a hydraulic support includes: determining a surrounding rock-support mutual feedback equilibrium curve under a first equivalent in-situ stress and a surrounding rock-support mutual feedback equilibrium curve under a second equivalent in-situ stress, according to the first equivalent in-situ stress, the second equivalent in-situ stress, a stress of a fracture zone on a softening zone under the first equivalent in-situ stress, and a stress of the fracture zone on the softening zone under the second equivalent in-situ stress; determining a support strength of a to-be-selected hydraulic support on the surrounding rock and a minimum expansion and contraction quantity required by a movable column according to the equilibrium curves; determining the residual burst energy that needs to be absorbed by the hydraulic support; and determining the hydraulic support matched with roadway.

Abstract: This disclosure discusses devices for mounting solar PV panels to a roof and other mounting structures. One device may include a railless mounting assembly that includes a roof attachment bracket and a panel attachment bracket. The roof attachment bracket may include a spring clip and a hook. The device may include a solar panel frame with built-in detents for mounting. It may include a solar panel frame capable of attaching to the spring clip and hook.

Abstract: Abstract: The present disclosure is directed to fusion proteins comprising a Tumor Necrosis Factor ? (TNF?) binding protein and an interleukin-10 (IL-10) molecule, methods of making the fusion proteins, and methods of treating or preventing autoimmune and inflammatory conditions using the fusion proteins.

Abstract: Provided is a phase-locked loop circuit, a method for configuring the same, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. The phase temperature compensation circuit includes at least one phase delay unit connected to the phase-locked loop main circuit and configured to generate a phase shift as a result of a temperature change for cancelling out a phase shift generated by the phase-locked loop main circuit as a result of a temperature change.

Abstract: A bracket for attaching solar panels to a roof, in the form of an L-foot, as well as devices and assemblies that utilize the L-foot. The L-foot includes a base and a riser extending upward from the base. The base includes a pair of raised stiffeners each extending obliquely upward toward each other from opposites sides of the base and each extending lengthwise along the base. The base can receive threaded roof fasteners that extend perpendicularly through the raised stiffeners and obliquely through the base. Threaded roof fasteners positioned on opposite raised stiffeners can extend through the roof deck toward each other. The L-foot is compatible with rail-based and rail-less solar panel racking systems.

Abstract: An electric power supply includes a totem pole bridgeless PFC power converter. The PFC power converter includes an input for coupling to an AC power source, an output, four switching devices coupled between the input and the output, two diodes coupled between the four switching devices and the input, a first inductor coupled between the four switching devices and the two diodes, and a second inductor coupled between the two diodes and the input. Other example electric power supplies and totem pole bridgeless PFC power converters are also disclosed.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

Abstract: An arbitration method, device, and computer-readable storage medium are provided. In an N-th clock cycle, P first requests respectively sent by P processing modules are obtained among M processing modules, where the M processing modules are each configured to send a first request to a memory module via an arbitration module, M is an integer greater than or equal to P, N is an integer greater than or equal to zero, and P is an integer greater than or equal to two. P timeslot values to be respectively allocated to IDs of the P processing modules are determined from a first timeslot table. A target request to be sent to the memory module in the N-th clock cycle is determined among the P first requests according to a normalized clock-cycle count corresponding to the N-th clock cycle and the P timeslot values.

Abstract: An image processing method, apparatus, and device, and a storage medium relate to the field of artificial intelligence. The method may include: obtaining an image corresponding to a target battery module, the target battery module including N solder joints, and the N solder joints being respectively mapped to N solder joint fields in the image; dividing the image according to the N solder joint fields to obtain N image regions in one-to-one correspondence with the N solder joint fields; calculating image difference information between each pair of adjacent image regions among the N image regions to obtain an image difference information set; and performing fault recognition on the target battery module based on the image difference information set. The accuracy for recognizing a preset fault in a battery module can be improved by the method.

Abstract: A handle for a prosthetic heart valve delivery apparatus includes a housing, a motorized mechanism, and a holding mechanism. The housing is configured to be hand-held by a user and includes a distal opening. The motorized mechanism is disposed within the housing and is configured to be releasably coupled to a proximal end portion of a first shaft of the prosthetic heart valve delivery apparatus. When actuated, the motorized mechanism is configured to rotate the first shaft relative to the housing. The holding mechanism is disposed inside the housing and is configured to engage a proximal end portion of a second shaft of the prosthetic heart valve delivery apparatus such that the second shaft is axially and rotationally fixed relative to the housing, and the first shaft extends through the second shaft.

Abstract: A filler for vacuum brazing of TU1 oxygen-free copper is an Au—Cu—Ni filler including the following elemental compositions in a specified proportion: 69% to 90% of Au, 9% to 30% of Cu, and 1% to 5% of Ni. The filler has a melting temperature of 900° C. to 910° C. The filler for vacuum brazing of TU1 oxygen-free copper can be used for brazing X-ray tube anodes, thereby realizing effective vacuum brazing.

Abstract: The present application describes antibody formulations, including monoclonal antibodies formulated in histidine-acetate buffer, as well as a formulation comprising an antibody that binds to domain II of HER2 (for example, Pertuzumab), and a formulation comprising an antibody that binds to DR5 (for example, Apomab).

Abstract: Disclosed herein are ink compositions that can be ink jetted onto a substrate with improved performance, low odor, and low migration properties. An example ink composition includes a mono-functional monomer, the mono-functional monomer including a hydrophilic mono-functional monomer; a di-functional monomer; an optional colorant; and an optional photoinitiator. Also disclosed are substrates decorated with a cured ink composition and methods of decorating a substrate with the ink compositions.

Abstract: The system monitors multiple communication channels between a first communicator and a second communicator. At least a portion of the multiple channels spatially overlap. The overlapping channels carry different communications. The system determines whether a first set of two or more channels among the multiple channels are interfering with each other. Upon detecting interference, the system obtains a first multiplicity of physical resource blocks associated with a first channel and a second multiplicity of physical resource blocks associated with a second channel, where a physical resource block comprises a frequency band of predetermined size. The system allocates a first subset of the first multiplicity of physical resource blocks to the first channel, and a second subset of the second multiplicity of physical resource blocks to the second channel, where the first subset and the second subset do not overlap.

Abstract: A laser level system including a laser level, the laser level projecting at least one laser line. The system also includes a bracket on which the laser level is mounted and a battery pack. The bracket includes a battery pack receptacle into which the battery pack is removably coupled. The battery pack powers the laser level. The battery pack has a maximum initial battery pack voltage (measured without a workload) of at least 18 volts. The system also includes at least one electrical conductor which delivers power from the battery pack in the battery pack receptacle to the laser level.

Abstract: Provided are a multi-core processing system and an inter-core communication method therefor, and a storage medium. The method includes: reading from a shared memory a message written by a transmitting core, and parsing the message to obtain a source address of and a data length of data to be transmitted (S102); performing storage space allocation based on the data length to obtain a destination address of the data to be transmitted (S104); and transmitting the data to be transmitted from a storage space corresponding to the source address to a storage space corresponding to the destination address by means of Direct Memory Access (DMA), based on the source address, the data length, and the destination address (S106).