Patents by Inventor Jun Lu

Jun Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190277867
    Abstract: Provided is an application of an artificially expressed HSP27 protein in detecting ?2-adrenergic receptor stimulant drug residue.
    Type: Application
    Filed: December 12, 2016
    Publication date: September 12, 2019
    Inventors: Fangyu WANG, Ruiguang DENG, Gaiping ZHANG, Xiaofei HU, Jing WANG, Qingxia LU, Guangxu XING, Qiuying YU, Jun LUO, Junfang HAO, Dong ZHAO, Jifei YANG
  • Patent number: 10411669
    Abstract: Volume leveler controller and controlling method are disclosed. In one embodiment, A volume leveler controller includes an audio content classifier for identifying the content type of an audio signal in real time; and an adjusting unit for adjusting a volume leveler in a continuous manner based on the content type as identified. The adjusting unit may configured to positively correlate the dynamic gain of the volume leveler with informative content types of the audio signal, and negatively correlate the dynamic gain of the volume leveler with interfering content types of the audio signal.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: September 10, 2019
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Jun Wang, Lie Lu, Alan J. Seefeldt
  • Patent number: 10412137
    Abstract: Embodiments of the present invention provide a video processing method, a mobile terminal, and a server. The method may include: sending, by a mobile terminal, a request to a server for pulling status update data of a social network, so that the server acquires original status update data that is requested to be pulled, the original status update data including a source video address; performing, by the server, adaptation processing on the source video address, to generate an adaptive video address; updating, by the server, the original status update data by using the adaptive video address, to obtain optimized status update data, and returning the optimized status update data to the mobile terminal; and obtaining, by the mobile terminal, adaptive video data according to the adaptive video address in the optimized status update data, and playing the adaptive video data.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: September 10, 2019
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Huixing Wang, Zhihao Wang, Junhong Huang, Yin Lu, Minghui Wang, Haiyou Li, Shang Yu, Jun Lin, Yi Liu, Jiancheng Lin
  • Patent number: 10410641
    Abstract: The present document describes a method (100) for extracting audio sources (301) from audio channels (302). The method (100) includes updating (102) a Wiener filter matrix based on a mixing matrix from a source matrix and based on a power matrix of the audio sources (301). Furthermore, the method (100) includes updating (103) a cross-covariance matrix of the audio channels (302) and of the audio sources (301) and an auto-covariance matrix of the audio sources (301), based on the updated Wiener filter matrix and based on an auto-covariance matrix of the audio channels (302). In addition, the method (100) includes updating (104) the mixing matrix and the power matrix based on the updated cross-covariance matrix of the audio channels (302) and of the audio sources (301), and/or based on the updated auto-covariance matrix of the audio sources (301).
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: September 10, 2019
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Jun Wang, Lie Lu, Qingyuan Bin
  • Patent number: 10407424
    Abstract: Naphthyridine compounds and their use as inhibitors of HPK1 are described. The compounds are useful in treating HPK1-dependent disorders and enhancing an immune response. Also described are methods of inhibiting HPK1, methods of treating HPK1-dependent disorders, methods for enhancing an immune response, and methods for preparing the naphthyridine compounds.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: September 10, 2019
    Assignee: Genentech, Inc.
    Inventors: Bryan Chan, Naomi Rajapaksa, Michael Siu, Craig Stivala, John Tellis, Weiru Wang, BinQing Wei, Aihe Zhou, Matthew W. Cartwright, Emanuela Gancia, Graham Jones, Blake Daniels, Michael Lainchbury, Andrew Madin, Eileen Seward, David Favor, Kin Chiu Fong, Andrew Good, Yonghan Hu, Baihua Hu, Aijun Lu, Joy Drobnick, Lewis Gazzard, Timothy Heffron, Malcolm Huestis, Jun Liang, Sushant Malhotra, Rohan Mendonca
  • Publication number: 20190273610
    Abstract: An example operation may include one or more of generating an initial seed and allocating one or more authorized bits of the initial seed to a plurality of blocks in a distributed ledger, storing the initial seed and an identification of which authorized bits of the initial seed are allocated to each block of the distributed ledger, receiving a final seed value that is partially generated by each of a plurality of nodes configured to access the distributed ledger based on authorized bits of respective blocks updated by each respective node, and generating a random sequence value based on the final seed value and storing the random sequence value in a block of the distributed ledger.
    Type: Application
    Filed: March 2, 2018
    Publication date: September 5, 2019
    Inventors: Si Bin Fan, David Kaminsky, Tao Liu, Jing Lu, Xiao Yan Tang, Jun Zhang
  • Patent number: 10402404
    Abstract: The present invention discloses a scheduling method and system based on a hybrid variable neighborhood search and gravitational search algorithm. The method includes: 1 setting parameters of the algorithm; 2 initializing an initial solution of the algorithm; 3 performing local search based on a gravitational search algorithm (GSA); 4 updating the initial solution; 5 determining whether an algorithm termination condition is satisfied; if yes, outputting the global optimal solution searched for by the algorithm, otherwise, returning to the step 3. According to the present invention, a near-optimal solution for the continuous batch processing problem based on position learning effect and linear starting time can be obtained, so that an enterprise can make full use of production resources thereof to the utmost extent, and thus reduce production costs and improve the enterprise service level and the customer satisfaction level.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 3, 2019
    Assignee: Hefei University of Technology
    Inventors: Jun Pei, Wenjuan Fan, Xinbao Liu, Qiang Zhang, Min Kong, Shaojun Lu
  • Patent number: 10401840
    Abstract: A method and a system for scheduling parallel machines based on hybrid shuffled frog leaping algorithm and variable neighborhood search algorithm are provided to solve collaborative production and processing of jobs on a plurality of unrelated batch processing machines. The jobs are distributed to machines based on the normal processing time and deterioration situation of the jobs on different machines and are arranged. An effective multi-machine heuristic rule is designed according to the structural properties of an optimal solution for the single-machine problem, and the improved rule is applied to the improved shuffled frog leaping algorithm to solve this problem. The improvement strategy for the traditional shuffled frog leaping algorithm is to improve the local search procedure of the traditional frog leaping algorithm by introducing the variable neighborhood search algorithm. The convergence rate and optimization capacity of the original algorithm are thus improved.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 3, 2019
    Assignee: Hefei University of Technology
    Inventors: Xinbao Liu, Jun Pei, Min Kong, Shaojun Lu, Xiaofei Qian, Zhiping Zhou
  • Publication number: 20190267172
    Abstract: Tapes and coils for superconducting magnets are provided, along with methods of making the tapes and coils. In one embodiment, the coil includes a rare earth barium copper oxide (REBCO) superconducting tape; and a thin resistive layer of copper oxide, Cr, Ni, or Ni—P substantially coated onto the REBCO superconducting tape, wherein the coated REBCO superconducting tape is wound into a coil form. In another embodiment, the coil includes at least two REBCO superconducting tapes; and a stainless steel tape interlay disposed between the at least two REBCO superconducting tapes, wherein the stainless steel tape comprises a plating layer of nickel or copper, and wherein the at least two REBCO superconducting tapes together with the stainless steel tape interlay are wound into a coil form.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 29, 2019
    Inventors: Jun Lu, Jeremy Levitan
  • Publication number: 20190266169
    Abstract: A system can comprise one or more processors; and one or more non-transitory computer-readable media storing computing instructions configured to run on the one or more processors and perform: receiving a request for a write operation of an input record in a data store associated with a sharded database and an alternate-key-global-index (AKGI) database; generating a new optimistic lock value, the new optimistic lock value being unique in the sharded database; when the data store does not include a data record associated with the input record, creating the dummy data record in the data store; locking the data record for the write operation by setting the DROpLock of the data record to the new optimistic lock value; and performing the write operation of the input record in the AKGI database and the sharded database.
    Type: Application
    Filed: February 28, 2019
    Publication date: August 29, 2019
    Applicant: Walmart Apollo, LLC
    Inventors: Jason Christopher Sardina, William R. Eschenbruecher, III, Jun Yi, Yi Lu, Nitin Chhabra, III, Ying Zhang, Alexei Olkhovskii, Robert Bruce Woods, III, Scott Melvin Harvester, Robert Perry Lowell
  • Patent number: 10396019
    Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, a metal slug, a plurality of spacers, a plurality of leads and a molding encapsulation. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the plurality of spacers. A bottom surface of the metal slug is exposed from the molding encapsulation. A process for fabricating the IPM comprises preparing the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar, the plurality of leads, the metal slug and the plurality of spacers and applying a molding process to form the molding encapsulation.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 27, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Zhiqiang Niu, Bum-Seok Suh, Wonjin Cho, Jun Lu
  • Patent number: 10397011
    Abstract: For logical multicasting in overlay networks, at a data processing system, an original unicast packet is received from a first component in a first computing node in an overlay network. To cause multicasting in the overlay network the received original unicast packet was unicast by the first computing node only to the data processing system, and a multicast data structure for the overlay network is maintained only by the data processing system, the multicast data structure containing information of each receiver that is configured to receive unicast packets during logical multicasting in the overlay network. From a set of subscriber receivers in the multicast data structure, a subset of the subscriber receivers is selected. A copy of the original unicast packet is unicast to each subscriber receiver in the subset.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing He, Jing Lu, Jun Yao
  • Publication number: 20190259719
    Abstract: A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hsiung Lu, Chen-Shien Chen, Chen-En Yen, Cheng-Jen Lin, Chin-Wei Kang, Kai-Jun Zhan
  • Patent number: 10377891
    Abstract: Resin compositions, layers, and interlayers comprising two or more poly(vinyl acetal) resins and at least one blending agent or haze reducing agent are provided. Such compositions, layers, and interlayers exhibit enhanced optical properties while retaining other properties, such as impact resistance and acoustic performance.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: August 13, 2019
    Assignee: Solutia Inc.
    Inventors: Wenjie Chen, John Joseph D'Errico, Jun Lu
  • Publication number: 20190244893
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, a plurality of NAND strings on the substrate, one or more peripheral devices above the NAND strings, a single crystalline silicon layer above the peripheral devices, and one or more interconnect layers between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng ZHU, Zhenyu LU, Jun CHEN, Yushi HU, Qian TAO, Simon Shi-Ning YANG, Steve Weiyi YANG
  • Publication number: 20190246466
    Abstract: A LED driving circuit and method for balancing efficiency and a power factor. The circuit comprises a voltage input module, an LED load, a constant current control module and a current turn-off slope control module for adjusting the turn-off slope of the current flowing through the LED load, such that a compromise between efficiency and power factor is achieved. When an input voltage is higher than a setting voltage, the current flowing through the LED load is turned off, such that the power consumption is reduced; in addition, the efficiency and power factor are balanced by adjusting the turn-off slope of the current. According to the present invention, a compensation capacitor is used to control the average current in an alternating current period and to limit peak current, thereby implementing constant power output within a wide range of input voltage.
    Type: Application
    Filed: December 30, 2016
    Publication date: August 8, 2019
    Applicant: CHINA RESOURCES POWTECH (SHANGHAI) CO., LTD.
    Inventors: JUN LIU, QUANQING WU, SHENGSHENG LU, GUOCHENG LI
  • Publication number: 20190244892
    Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate, The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 10372761
    Abstract: In an example, one or more processes that transform data originating in one or more of a plurality of different data sources are identified. Then, for each of the identified one or more processes, a relationship table is created, the relationship table listing objects input to the process, objects output from the process, and one or more mappings defining transformations performed on the objects input to the process to produce the objects output from the process. Dependencies are created between relationship tables by linking at least an instance of a first object input to a process in a first relationship table with at least an instance of the first object output from a process in a second relationship table. Lineage of an object in the computer system is traced by accessing one or more of the relationship tables and the dependencies.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: August 6, 2019
    Assignee: SAP SE
    Inventors: Min He, Nikhil Patil, Jun Lu
  • Patent number: 10372867
    Abstract: Techniques for analyzing a routed interconnection of a net of a circuit are discussed herein. Some embodiments may include a method comprising with a computer, analyzing the circuit to determine a performance parameter of the net, wherein the circuit is analyzed based at least in part on applying pre-layout simulation data of the net to layout data of the circuit. Additionally or alternatively, the circuit may be analyzed based on extracting characteristics of the routed interconnection from the layout data of the net.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 6, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Jun Wang, Randy Bishop, Jingyu Xu, Dick Liu, Hu Cai, Jun Lu
  • Publication number: 20190232624
    Abstract: Multilayered interlayers comprising stiff skin or outer layers and a soft core layer(s) are disclosed. The multilayered interlayers comprise: a first polymer layer (skin layer) comprising plasticized poly(vinyl butyral) resin; a second polymer layer (core layer) comprising a blend of two (or more) plasticized poly(vinyl butyral) resins having different residual hydroxyl content; and optionally a third polymer layer (skin layer) comprising plasticized poly(vinyl butyral) resin.
    Type: Application
    Filed: March 25, 2019
    Publication date: August 1, 2019
    Applicant: Solutia Inc.
    Inventor: Jun Lu