Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

Abstract: The present invention provides an electrode running roller which causes an electrode sheet in which a current collector is coated with an electrode active material to run, wherein the running roller includes a cylindrical section, and a tapered section extending from one end portion of the cylindrical section, and the tapered section has a shape in which an outer diameter gradually decreases toward a distal end portion of the tapered section.

Abstract: A temperature sensing device and a temperature sensing method are provided. The temperature sensing device includes a sensor and a conversion circuit. The sensor generates a first sensing signal and a second sensing signal corresponding to a temperature based on different conditions. The conversion circuit performs a subtraction operation on the first sensing signal and the second sensing signal to obtain a result difference value, calculates a compensation value according to the result difference value and the first sensing signal, multiplies the result difference value and the compensation value to obtain a multiplication value, subtracts the multiplication value from the first sensing signal to generate a first value, adds the multiplication value to the first sensing signal to generate a second value, and divides the first value by the second value to generate an output value. The second value is a constant.

Abstract: A request to perform a program operation to program a set of memory cells on a memory device is received. A defect indicator associated with the set of memory cells is determined to satisfy a defect condition. A value of a program verify parameter is determined based on the defect indicator. The program operation is performed using the value of the program verify parameter during a program verify phase of the program operation.

Abstract: A method for partial block read compensation can include receiving a read request that specifies a memory cell connected to a string of series-connected memory cells in an array of memory cells on a memory device, the string located at an intersection of a wordline and a bitline, and causing a first voltage applied to the wordline to which the specified memory cell is connected to ramp to a first predetermined value. The method can include causing a second voltage applied to the bitline to which the specified memory cell is connected to ramp to a second predetermined value, and can include comparing, using a current comparator, a current along the string with a reference current to generate an analog output signal. It can also include causing a voltage offset, based on the analog output signal, to be applied to a read voltage level during a sensing operation.

Abstract: The present disclosure provides a system and method for medical image visualization. The method may include obtaining original image data of a subject, the original image data including a first region of interest (ROI) and a second ROI. The method may also include generating first image data associated with the first ROI according to a first instruction, and causing the first ROI to be displayed on a display device as a first image based on the first image data. The method may further include generating, according to a second instruction, second image data corresponding to a target region that includes the second ROI, updating the first image data based on the second image data, and causing the second ROI to be displayed on the display device as a second image based on the updated first image data.

Abstract: The present invention relates to an electrode assembly laminating roller for laminating an electrode and a separator, wherein the laminating roller comprises a central portion; and end portions positioned at both ends of the central portion with respect to the longitudinal direction, and wherein the surface temperature of the end portion is expressed higher than the surface temperature of the central portion.

Abstract: A memory system identifies memory cells connected to a common word line that have had their threshold voltage unintentionally drift lower than programmed by determining whether memory cells meet two criteria: (1) the memory cells have threshold voltages within an offset of a read compare voltage of a data state; and (2) adjacent memory cells (connected to word lines that are adjacent to the common word line) are in one or more low data states. For those memory cells meeting the two criteria, the memory system performs some amount of programming on the memory cells to refresh the data stored in those memory cells to be as originally intended.

Abstract: A pressurizing channel includes a pair of pressurizing plates disposable on opposite sides of a secondary battery with the secondary battery interposed therebetween. Each pressurizing plate includes a body part and an exterior part connected to opposite ends of the body part, each exterior part including a tube inside that is expandable by hydraulic pressure. An apparatus for charging and discharging a secondary battery having a plurality of pressurizing channels is also provided.

Abstract: Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.

Abstract: In some implementations, a controller of a memory device may obtain a first metric associated with a memory of the memory device using a first memory read configuration. The controller may apply a function to the first metric to obtain a second memory read configuration. The controller may obtain a second metric associated with the memory using the second memory read configuration. The controller may filter the first metric and the second metric to obtain a first filtered metric and a second filtered metric. The controller may provide the first filtered metric and the second filtered metric to a memory management process executing on the controller. The controller may perform an action based on an output of the memory management process, wherein the output is based on the first filtered metric and the second filtered metric.

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. The set of memory components includes a processing device that initiates a corrective read (CR) operation on a set of memory components. The set of memory components includes a pillar that includes a channel and a plurality of transistors. The processing device applies a charge to a first word line (WL) comprising a first transistor of a plurality of transistors to neutralize charges in the channel and senses a charge distribution of a second WL comprising a second transistor of the plurality of transistors adjacent to the first transistor based on the charge applied to the first WL that neutralized the charges in the channel.

Abstract: A pressurizing channel includes a pair of pressurized plates disposable on opposite sides of a secondary battery with the secondary battery interposed therebetween. Each pressurizing plate includes a body part formed with a material that has a first coefficient of thermal expansion; and an exterior part that connects to opposite ends of the body part and includes a thermal expansion part containing a material that has a second coefficient of thermal expansion, which is greater than the first coefficient of thermal expansion. An apparatus for charging and discharging a secondary battery having a plurality of pressurizing channels is also provided.

Abstract: The present disclosure relates to a networked ecological conservation water-saving system for urban mass green land, comprising 5-9 ecological conservation water-saving devices which are orderly arranged in the urban green land per square meter. The ecological conservation water-saving devices are arranged in a central symmetry manner. Each ecological conservation water-saving device comprises a columnar housing and an infiltrating irrigation unit. A first water storage unit is provided at the center of each infiltrating irrigation unit, and a second water storage unit is provided at the lower part of each first water storage unit. The networked ecological conservation water-saving system further comprises a first water delivery pipe network, a second water delivery pipe network, and a third water delivery pipe network.

Abstract: The chip package structure includes a bare chip, a bare chip carrier, and a package body. The bare chip is located on one side of the bare chip carrier. The package body covers the bare chip to package the bare chip on the bare chip carrier. A recess structure is provided on an outer surface of the package body. The recess structure is configured to increase a heat dissipation area of the package body. The recess structure increases a surface area of the package body, and therefore increases the heat dissipation area of the package body, thereby enhancing a heat dissipation capability of the package body.

Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

Abstract: A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.

Abstract: The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block using the second erase verify level; and identify, based on the determination, whether the block has failed.

Abstract: Systems and methods for image rendering are provided. The methods may include: rasterizing a primitive to determine rendering parameters of primitive pixel points representing the primitive in a target image; determining depth of volume data pixel points representing volume data in a preset region in the target image; and performing a physical rendering operation on the volume data to obtain the target image based on the depth of the volume data pixel points, color information of the volume data pixel points, and the rendering parameters, wherein the rendering parameters at least include depth of the primitive pixel points and color information of the primitive pixel points.