Abstract: A stemless operation mechanism includes a case, a first moving component, a second moving component and a detection module. The case includes a first accommodating area, a second accommodating area and a partition portion used to provide an airtight isolating function. The first moving component is movably disposed on the first accommodating area and includes a first magnetic unit. The second moving component is movably disposed on the second accommodating area and includes a second magnetic unit located on position corresponding to position of the first magnetic unit. The second magnetic unit is cooperated with the first magnetic unit to generate a magnetic attraction force or a magnetic repulsion force. The detection module is disposed adjacent to the second moving component, and adapted to detect a movement of the second moving component for determining an operation behavior applied for the first moving component.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a bit line located on the substrate; and a support layer located on the substrate, wherein the support layer includes a first support segment and a second support segment, the first support segment and the second support segment are both connected to the bit line, and the bit line is located between the first support segment and the second support segment.

Abstract: Provided is a preparation method of a semiconductor device, including the following steps: providing a substrate and forming a mask layer with a plurality of first windows on the substrate; forming a dielectric layer, the dielectric layer at least covering sidewalls of the first windows; forming a first photoresist material layer, the first photoresist material layer covering the dielectric layer and the mask layer and filling the first windows; patterning the first photoresist material layer to form a patterned first photoresist layer which exposes a top surface of the dielectric layer; by using the first photoresist layer and the mask layer as masks, removing the dielectric layer to form second windows; and removing part of the substrate along the second windows to form a patterned substrate.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure, including: an insulating layer includes a first dielectric layer and a second dielectric layer, a protective layer covers an upper surface of the second dielectric layer and a bottom and sidewalls of the first trench; removing part of the protective layer to expose at least part of a surface of the second dielectric layer; removing the second dielectric layer by a first wet etching process, the first wet etching process has a first etch selectivity of a material of the second dielectric layer to that of the first dielectric layer; and removing the protective layer by a second wet etching process, the second wet etching process has a second etch selectivity of a material of the protective layer to that of the first dielectric layer, and the second etch selectivity is greater than the first etch selectivity.

Abstract: An embodiment of the application provides a method for forming a semiconductor structure. The semiconductor structure includes a first region and a second region. The method includes the following steps: providing a base, an insulating layer, and a mask layer that are stacked in sequence, where the first region has at least one trench penetrating the mask layer and the insulating layer, and the mask layer has an upper surface in the second region higher than that in the first region; forming a first protection layer, where an upper surface and a sidewall of the mask layer in the first region are covered with the first protection layer; after the first protection layer is formed, removing the mask layer in the second region; subsequent to removal of the mask layer in the second region, removing the first protection layer; and removing the mask layer in the first region.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method for manufacturing a semiconductor structure includes: forming a conductive layer, a protective layer, and a mask layer in sequence on the substrate, the mask layer including a first pattern facing the first region and a second pattern facing the second region; forming a restriction pattern located in the second region by etching the protective layer using the mask layer as a mask; and forming contact pads located in the first region and connecting wires located in the second region on the conductive layer by etching the conductive layer using the mask layer as a mask.

Abstract: A method for manufacturing a mask structure includes: patterning a sacrificial layer and a second dielectric layer, so as to form pattern structures each including a first pattern and a second pattern, and a width of a lower portion of the pattern structures is less than a width of a upper portion of the pattern structures; forming an initial mask pattern on sidewalls of each of the plurality of pattern structures; filling a first filling layer between adjacent initial mask patterns located on the sidewalls of different pattern structures; removing the second patterns and the initial mask pattern located on sidewalls of each of the plurality of second patterns; removing the first filling layer and the first patterns, so as to form first mask patterns; and forming second mask patterns on the first mask patterns.

Abstract: This application provides an authentication credential protection method and system. The protection method includes the following steps: generating authentication secret information based on a lock screen password and hardware secret information of a first device; randomly generating, by the first device, a symmetric key, and using the symmetric key as an encryption key for the authentication secret information; splitting the encryption key into at least two first key segments by using a multi-party data splitting algorithm, where one of the at least two first key segments is stored on the first device; and sending, by the first device, another first key segment to a trusted device. In the foregoing technical solution, the authentication secret information is generated by using the lock screen password and the hardware secret information, increasing information complexity. In addition, different trusted devices are used to store the split key segments, improving security of the encryption key.

Abstract: A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.

Abstract: A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

Abstract: The present application provides a method and a device for encryption of a video stream, a communication equipment, and a storage media. The method for encryption of a video stream includes: acquiring a video stream, encrypting a data part of an I frame by using a first encryption algorithm to obtain a first encrypted data, and encrypting an encryption key of the first encrypted data by using a second encryption algorithm to obtain a second encrypted data, and storing the second encrypted data in a frame header of the I frame to obtain an encrypted I frame.

Abstract: Embodiments provide a memory and a fabrication method thereof, and relates to the field of storage device technology to solve the technical problem of lower storage density of the memory. The fabrication method of the memory includes: providing a substrate including a central region and an edge region connected to each other, a first contact structure electrically connected to a wordline structure in the substrate being formed in the edge region; forming a second contact structure electrically connected to the first contact structure on the edge region; forming a capacitor structure electrically connected to the wordline structure on the central region; forming a third contact structure electrically connected to the second contact structure on the second contact structure; and forming a transistor structure electrically connected to the wordline structure on the capacitor structure and the third contact structure.

Abstract: An embodiment of the disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, where the substrate has a peripheral region and an array region; stacking and forming an insulating layer and a mask layer with a mask pattern on the substrate; etching the insulating layer with the mask layer as a mask to form a contact hole penetrating the insulating layer at the array region; reserving the mask layer; in a direction perpendicular to a surface of the substrate, providing a thickness difference between the mask layer of the peripheral region and the mask layer of the array region; forming a first material layer; forming a second material layer; etching a part of the mask layer with the second material layer as the mask; and removing the remaining second material layer, the remaining mask layer and the first material layer on the remaining mask layer.

Abstract: A method for manufacturing a memory includes: providing a substrate, capacitor contact pads being formed in the substrate; forming a laminated structure on the substrate, the laminated structure including a first laminated structure formed on the substrate and a second laminated structure formed on the first laminated structure; forming first through holes in the second laminated structure; forming a protective layer on side walls of the first through holes, the protective layer in the first through holes enclosing second through holes; and etching the first laminated structure along the second through holes to form third through holes, the third through holes exposing the capacitor contact pads.

Abstract: A method for manufacturing a memory and a memory is provided. The method for manufacturing a memory includes: providing a substrate; stacking an electrode support structure, a protective layer and a first mask layer in sequence on the substrate; patterning the first mask layer on an array region, and etching the protective layer, the electrode support structure and the substrate by using the patterned first mask layer as a mask, to form capacitor holes penetrating the protective layer and the electrode support structure and extending into the substrate; removing the first mask layer; and forming a first electrode layer on side walls and bottom walls of the capacitor holes, a top surface of the first electrode layer being flush with a top surface of the electrode support structure.

Abstract: An electrochemical apparatus includes a first housing, a second housing, a cell assembly, a first circuit board, a heat dissipating portion, a protrusion, and a fixing member. The first housing and the second housing are connected to form an accommodation space. The cell assembly, the first circuit board, and the fixing member are disposed in the accommodation space, and the cell assembly is connected to the first circuit board. The first circuit board includes an electronic component, the electronic component includes a heat conducting portion, and the heat conducting portion is connected to the protrusion. The heat dissipating portion is disposed outside the accommodation space and connected to the first housing, and the protrusion is connected to the heat dissipating portion. The fixing member is fixed on the first housing, and the heat conducting portion is partly located between the protrusion and the fixing member.

Abstract: Embodiment relates to a method for fabricating a semiconductor structure. The method includes: forming a first pattern on the first region and forming a second pattern on the second region, wherein the first pattern includes a plurality of first sub-patterns, a first gap is provided between adjacent two of the plurality of first sub-patterns, a width of the first gap is a first pitch, and wherein the second pattern includes a plurality of second sub-patterns, a second gap is provided between adjacent two of the plurality of second sub-patterns, a width of the second gap is a second pitch, and the second pitch is greater than the first pitch; forming a first mask layer on a sidewall of the first pattern, and forming a second mask layer on a sidewall of the second pattern; and removing the first pattern and the second pattern.

Abstract: A method for forming a capacitor array structure includes the following operations. A base is formed, which includes a substrate, a stack structure located on the substrate and a mask layer located on the stack structure in which an etching window that penetrates the mask layer in a direction perpendicular to the substrate is provided. The stack structure is etched along the etching window to form a capacitor hole that penetrates the stack structure along the direction perpendicular to the substrate. A conductive layer that fills up the capacitor hole and the etching window and covers a top surface of the mask layer is formed. The conductive layer and the mask layer at a top surface of the stack structure are removed, and the conductive layer remaining in the capacitor hole forms a lower electrode.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate; forming a first mask layer with a first pattern on the stack; forming a first photoresist layer on the first mask layer; exposing the first photoresist layer, and developing to remove the first photoresist layer on the complete die region; and etching the stack by using the first mask layer on the complete die region and the first photoresist layer on the incomplete die region as masks.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a base, wherein the base is provided with an active region; forming a gate layer on the base; forming isolation structures on a periphery of the gate layer, wherein in a direction away from the gate layer, each of the isolation structures at least includes a hollow portion and an isolation portion; forming an insulating structure on top surfaces of the isolation structures; forming contact plugs, wherein the contact plugs penetrate the insulating structure; an end of each of the contact plugs close to the base is electrically connected to the active region; each of the contact plugs is located on a side of each of the isolation structures away from the gate layer.