Abstract: A memory device having a high bus efficiency on a network, an operating method of the memory device, and a memory system including the memory device are provided. The memory device includes banks, a programming register, and a controller. Each of the banks has a plurality of memory cells arranged in a matrix of rows and columns. In a write operation, the programming register stores simultaneous write information on how many banks there are in which data are stored. In a read operation, the controller selects one of the banks subjected to the write operation in response to the simultaneous write information to read out the memory cell data in the selected bank.

Abstract: Provided are a semiconductor memory device and system in which a refresh flag is generated. The semiconductor memory device includes an oscillator for generating an oscillator output signal; a refresh timer for generating a refresh pulse in response to predetermined first and second control signals, the oscillator output signal, and an external clock signal; a mode register set (MRS) unit for generating the first and second control signals in response to an address signal and an external command, the first control signal controlling time when the refresh pulse is generated by the refresh timer and the second control signal resetting the refresh timer; and a refresh controller for generating a refresh control signal in response to the refresh pulse, the refresh control signal refreshing a memory cell, wherein the refresh control signal is output as a refresh flag while the memory is refreshed.

Abstract: Integrated circuit memory devices include a memory cell array having therein a plurality of stored data bits and a plurality of parity bits generated from a plurality of write data bits received by the memory device during a write operation. The plurality of stored data bits and the plurality of parity bits may collectively form a word having a length of m+p bits, where m and p are integers. An error check circuit is provided that converts the plurality of stored data bits and the plurality of parity bits into a plurality of syndrome bits (e.g., Si) that designate a location of a bit error in the plurality of stored data bits when compared against the original write data bits. An error correction circuit is provided that uses the plurality of syndrome bits to correct an error in the plurality of stored data bits and generate a plurality of read data bits that match the plurality of original write data bits.

Abstract: A semiconductor integrated circuit and a memory device capable of selecting power-down exit speed and power-save modes and method thereof are provided. The memory device includes a command decoder for generating a power-down signal in response to a power-down command, a mode register (MRS) for storing power-down exit information, a clock synchronization circuit such as a DLL or PLL circuit for generating an internal clock signal synchronized with an external clock signal, and a controller for controlling the DLL or PLL circuit. At power-down exit of the memory device, the power-down exit information can be selected between a fast wakeup time and a slow wakeup time.

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract: A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit. A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.

Abstract: A semiconductor memory device capable of improving common bus efficiency is disclosed. The device comprises an address shifting circuit for delaying an address by an n+m number of clock cycles in response to a clock signal, a control signal generating circuit for combining a column address strobe (CAS) latency of n-value and one of first and second operation signals to generate a control signal, and a switching circuit for outputting the address delayed by the n+m number of clock cycles output from the address shifting circuit in response to the control signal. The first operation signal indicates that the n-value of the CAS latency is less than a predetermined value and write latency is fixed. The second operation signal indicates that the n-value of the CAS latency is equal to or greater than the predetermined value and the write latency is variable.

Abstract: The semiconductor memory device includes local input/output (I/O) lines, global I/O lines, and a memory corethat is coupled between a bit line and a complementary bit line. The memory core includes a memory cell array, a bit line equalizer circuit, a PMOS sense amplifier (S/A), a PMOS S/A driving circuit for driving the PMOS S/A, a transmission gate circuit, an NMOS S/A, and an NMOS S/A driving circuit for driving the NMOS S/A. First and second transistors for connecting the local I/O lines to the global I/O lines are installed between adjacent bit lines. The PMOS S/A driving circuit, which is a first driving transistor, and the NMOS S/A driving circuit, which is a second driving transistor, are also installed between adjacent bit lines. Because the semiconductor memory device arranges a PMOS S/A driving circuit, an NMOS S/A driving circuit, and a gating circuit for connecting local I/O lines to global I/O lines, between adjacent bit lines, the chip area is reduced.

Abstract: The present invention provides a system board and an impedance control method thereof. The board includes a plurality of modules or devices, and a control apparatus for controlling the modules or devices. Signal lines are connected from the control apparatus to the plurality of modules or devices and are arranged so that the length of the signal lines between the control apparatus and the plurality of modules or devices becomes shorter the distance from the control apparatus increases. Therefore, the present invention can reduce the signal distortion phenomenon by controlling the characteristic impedance of the signal lines between the control apparatus and the plurality of modules or devices such that the characteristic impedance decreases exponentially with increasing distance from the control apparatus in the case in which modules or devices are plugged into the system board.

Abstract: A semiconductor memory device is provided in which a burst length and/or a column address strobe (CAS) latency may be fixed. The semiconductor memory device, which may be an SDRAM (synchronous dynamic random access memory) device, includes a memory cell array, a burst address generation circuit to generate a burst address and a burst length detection signal, a mode setting register for setting a CAS latency and/or a burst length using an address, a pipeline circuit to delay and output data read from the memory cell array. The semiconductor memory device also includes a latency enable control signal generation circuit to generate a latency enable control signal in response to a read command or signal and the burst length detection signal, and a data output circuit to output data being output from the pipeline circuit in response to the latency enable control signal. Therefore, a circuit configuration is simplified and a test time is reduced, by fixing latency and/or burst length.

Abstract: A semiconductor memory device capable of improving common bus efficiency is disclosed. The device comprises an address shifting circuit for delaying an address by an n+m number of clock cycles in response to a clock signal, a control signal generating circuit for combining a column address strobe (CAS) latency of n-value and one of first and second operation signals to generate a control signal, and a switching circuit for outputting the address delayed by the n+m number of clock cycles output from the address shifting circuit in response to the control signal. The first operation signal indicates that the n-value of the CAS latency is less than a predetermined value and write latency is fixed. The second operation signal indicates that the n-value of the CAS latency is equal to or greater than the predetermined value and the write latency is variable.

Abstract: A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit. A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.

Abstract: A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit. A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks each including a plurality of partial blocks, a plurality of global word lines, and odd-numbered and even-numbered sub word lines corresponding to each of the plurality of the global word lines, the odd-numbered sub word lines of each of odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the previous neighboring partial blocks, the even-numbered sub word lines of each of the odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the even-numbered sub word lines of each of the next neighboring partial blocks, the odd-numbered sub word lines of each of even-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the next neighboring partial blocks, the even-numbered sub word lines of each of the even-numbered partial blocks

Abstract: Integrated circuit memory devices include first and second memory banks, first and second local data lines electrically coupled to the first and second memory banks, respectively, and a multiplexer having first and second inputs electrically coupled to first and second data bus lines, respectively. A data selection circuit is also provided which routes data from the first and second local data lines to the first and second data bus lines, respectively, when a selection control signal is in a first logic state and routes data from the second and first local data lines to the first and second data bus lines, respectively, when a selection control signal is in a second logic state opposite the first logic state. A control signal generator is also provided. This control signal generator generates the selection control signal in the first and second logic states when a first address in a string of burst addresses is even and odd, respectively.

Abstract: A signal is duty-cycle corrected by delaying the signal to generate a delayed version of the signal and generating an output signal that transitions from a first state to a second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state. The output signal transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.

Abstract: A circuit for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.

Abstract: A semiconductor memory device comprising control pads and input/output I/O pads capable of reducing the data path for reading and writing data in a cell array, and a method for driving the semiconductor memory device are included. The semiconductor memory device comprises a plurality of memory banks arranged at a cell region of a memory chip, and a plurality of control pads and a plurality of I/O pads, separately arranged from each other at the memory chip, for reading/writing data from/in the memory banks, wherein the plurality of control pads and I/O pads are dispersed at the peripheral region between adjacent memory banks and at the outer portions of the memory banks.

Abstract: An input buffer includes an amplifier circuit, such as a differential amplifier circuit, inverting amplifier circuit or pull-up/pull-down amplifier circuit. A momentary boost circuit is coupled to an input buffer input terminal, an input terminal of the amplifier circuit, and an output terminal of the amplifier circuit, and is operative to generate a boosted input signal at the input terminal of the amplifier circuit from an input signal at an input buffer input terminal for an interval that is terminated responsive to an output signal at the output terminal of the amplifier circuit.

Abstract: An internal voltage generation circuit is provided which can stably generate an internal supply voltage even if an external supply voltage decreases. The internal voltage generation circuit includes first and second level shifters, a differential amplifier and a driver. The first level shifter is connected to an internal supply voltage terminal and lowers the internal supply voltage to a predetermined voltage level. The second level shifter is connected to a reference voltage terminal and lowers a reference voltage to a predetermined voltage level. The differential amplifier compares the output voltage of the second level shifter with the output voltage of the first level shifter and amplifies the difference between the two output voltages. The driver generates the internal supply voltage in response to the output of the differential amplifier.