Abstract: An internal clock signal generator is provided which includes a synchronized delay circuit which receives an external clock signal and outputs a clock signal which is coarsely synchronized with the external clock signal. A delay locked loop (DLL) or phase locked loop (PLL) receives the coarsely synchronized clock signal and generates an internal clock signal which is more finely synchronized with the external clock signal.

Abstract: A semiconductor memory device is provided that is capable of increasing a data processing speed and the efficiency of a data input and output pin. A method is also provided for controlling the read and write of such a device. A data first-in first-out (FIFO) circuit temporarily stores write data when a read command is received during a write operation and outputs the stored write data to the memory cell array after a read operation is completed. An address FIFO circuit temporarily stores addresses corresponding to the write data when the read command is received during the write operation and outputs the stored addresses to the memory cell array after the read operation is completed. A control signal generator generates a plurality of control signals for controlling the data FIFO circuit and the address FIFO circuit in response to a write command and the read command.

Abstract: A signal transmission circuit and a method equalize differential delay characteristics of two signal transmission lines. A controllable delay unit is connected serially to the second line, so as to compensate by adding its internal delay. An auxiliary signal transmission line replicates the second transmission line, while it processes the input signal of the first. A controlling unit compares the output signal of the first transmission line and the of the auxiliary signal transmission line, and adjusts dynamically the internal delay of the controllable delay unit, to attain continuous synchronization. A data latch circuit synchronizes the delays of data paths by having one controllable delay units in each of the data paths.

Abstract: The present invention provides a system board and an impedance control method thereof. The board includes a plurality of modules or devices, and a control apparatus for controlling the modules or devices. Signal lines are connected from the control apparatus to the plurality of modules or devices and are arranged so that the length of the signal lines between the control apparatus and the plurality of modules or devices becomes shorter the distance from the control apparatus increases. Therefore, the present invention can reduce the signal distortion phenomenon by controlling the characteristic impedance of the signal lines between the control apparatus and the plurality of modules or devices such that the characteristic impedance decreases exponentially with increasing distance from the control apparatus in the case in which modules or devices are plugged into the system board.

Abstract: A signal is duty-cycle corrected by delaying the signal to generate a delayed version of the signal and generating an output signal that transitions from a first state to a second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state. The output signal transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.

Abstract: Integrated circuit memory devices that utilize preferred masking techniques include a memory cell array and a mask signal generator that generates first and second internal data masking signals in response to at least one single data rate mode signal. A data controller is also provided to pass input write data to the memory cell array when the first and second internal data masking signals are inactive and mask at least a portion of the input write data from the memory cell array when one of the first and second internal data masking signals is active. This ability to mask data facilitates operation of the memory device in a specialized single data rate mode for testing using conventional test equipment.

Abstract: A synchronous DRAM (SDRAM) having a posted column access strobe (CAS) latency and a method of controlling CAS latency are provided. In order to control a delay time from the application of a CAS command and a column address to the beginning of memory, reading or writing operations in units of clock cycles, a first method of programing the delay time as a mode register set (MRS) and a second method of detecting the delay time using an internal signal and an external signal, are provided. In the second method, the SDRAM can include a counter for controlling the CAS latency. This counter controls the CAS latency of the SDRAM by generating a signal for controlling the CAS latency according to the number of clock cycles of a clock signal from the generation of a row access command to a column access command in the same memory bank and reading the signal.

Abstract: A semiconductor memory device is provided having reduced power consumption during a normal operation. The semiconductor memory device includes a sub word-line defined by segmenting a word-line and a driving signal generator for selectively driving the sub word-line according to a column address. The driving signal generator is controlled by a selection signal corresponding to the column address and a mode signal for specifying an operation mode of the semiconductor memory device. The semiconductor memory device enables part of the word-line according to the column address. The semiconductor memory device using a sub word-line driver to reduce the number of memory cells which are sensed, thereby reducing power consumption.

Abstract: Programmable delay lines include a delay circuit having an input and a plurality of outputs which each provide a respective delayed version of a periodic input signal provided to the input. A delay switch is also provided to pass at least one of the plurality of outputs of the delay circuit to a switch output, in response to a digital control signal (P1-Pn). A preferred phase comparing circuit is also provided. This phase comparing circuit compares the input signal against the delayed versions of the input signal (at the plurality of outputs) and generates a digital phase signal (F1-Fn) that identifies which of the delayed versions of the input signal is in-phase with the input signal. The programmable delay line also includes a pointer which generates the digital control signal in response to the digital phase signal and a plurality of pointer control signals (S0, S1 and WS).

Abstract: Integrated circuit devices include a data buffer that is responsive to a control signal, enabled to pass data received at a data input thereof to a data output thereof when the control signal is in an active logic state and disabled to block passage of data from the data input to the data output when the control signal is in an inactive logic state. A data buffer control circuit is also provided. The data buffer control circuit latches a latency signal in response to a control clock, generates the control signal from the latched latency signal and comprises a pulse generator that drives the control signal to its inactive logic state in-sync with an edge of the latency signal. This inactive control signal can be used to disable the data buffer.

Abstract: Integrated circuit devices having synchronized signal generators therein include a first signal generator and a second signal generator. The first signal generator receives a first input signal and a complementary version of the first input signal at true and complementary inputs thereto, respectively, and generates a first output signal having a leading edge in-sync with a leading edge of the first input signal (e.g., clock signal CLK) but delayed relative thereto by a first time interval. The second signal generator receives the first input signal and the complementary version of the first input signal at complementary and true inputs thereto, respectively, and generates a second output signal having a leading edge in-sync with a leading edge of the complementary version of the first input signal but delayed relative thereto by the first time interval. First and second pulse generators are also preferably provided.

Abstract: A column select circuit capable of minimizing load to data input/output lines, a semiconductor memory device having the same, and an arrangement method for the semiconductor memory device are described. In the semiconductor memory device having column select circuits, each column select circuit selects one of at least two banks in a memory block and selects a predetermined bit line among a plurality of bit lines in the selected bank to transfer data of the selected bit line to data input/output line. The column select circuit includes one or more first select portions for connecting the bit lines of the selected bank to the corresponding first data lines in response to a bank select signal to select a predetermined bank. One or more second select portions connects the first data lines to a second data line in response to each column select signal which represents the address of each bit line.

Abstract: A column address decoder for two bit prefetch of a semiconductor device and a decoding method thereof are provided. The column address decoder includes a memory cell array having a plurality of memory cells for storing data and redundancy memory cells for replacing poor memory cells, a plurality of bit lines connected to the memory cells, a plurality of input and output lines, a plurality of switching means connected between the bit lines and the input and output lines.

Abstract: Integrated circuit memory devices that utilize preferred masking techniques include a memory cell array and a mask signal generator that generates first and second internal data masking signals in response to at least one single data rate mode signal. A data controller is also provided to pass input write data to the memory cell array when the first and second internal data masking signals are inactive and mask at least a portion of the input write data from the memory cell array when one of the first and second internal data masking signals is active. This ability to mask data facilitates operation of the memory device in a specialized single data rate mode for testing using conventional test equipment.

Abstract: Integrated circuit memory devices include first and second memory banks, first and second local data lines electrically coupled to the first and second memory banks, respectively, and a multiplexer having first and second inputs electrically coupled to first and second data bus lines, respectively. A data selection circuit is also provided which routes data from the first and second local data lines to the first and second data bus lines, respectively, when a selection control signal is in a first logic state and routes data from the second and first local data lines to the first and second data bus lines, respectively, when a selection control signal is in a. second logic state opposite the first logic state. A control signal generator is also provided. This control signal generator generates the selection control signal in the first and second logic states when a first address in a string of burst addresses is even and odd, respectively.

Abstract: An internal clock generator including a switching controller interposed between a digital delay locked loop and an externally generated clock signal. The switching controller reduces current consumptions starting from a next cycle when an external clock and an internal clock are in phase. Further, when the external clock and the internal clock are in phase, driving of the unnecessary elements is suppressed, thereby reducing the current consumption in the internal clock generator.

Abstract: A circuit and method are described for transferring data in a semiconductor memory in synchronism with a reference clock. A data transfer circuit according to the invention includes a non-overlapping clock generator, a data output circuit, and a data input circuit. The non-overlapping clock generator generates a plurality of non-overlapping clock signals, each of which is active during a different time interval during a period of one external clock cycle. The data output circuit selects and outputs a selected one of a plurality of internal data signals in response to an active one of the non-overlapping clock signals. The data input circuit then receives the selected one of the internal data signals and outputs it to the semiconductor memory in response to the active one of the non-overlapping clock signals.

Abstract: Disclosed is a synchronous semiconductor device having a double data rate input circuit which allows data to be written in the device in response to a clock signal and a data strobe signal. The input circuit stores a pair of data which is synchronized with either the clock signal or the data strobe signal, thereby processing data at high speed. In case the data strobe is used, data setup and hold window margin is improved.

Abstract: A bidirectional input/output buffer operates in a current mode to increase the data transfer rate between devices connected by a bidirectional transmission line. The buffer includes an output current source for generating an output current responsive to a data output signal. The output current is combined with an output current indicative of a data input signal received from another device over a transmission line, thereby forming a mixed current signal. The data input signal is restored from the mixed signal by a restoring circuit that compares the mixed signal to a reference current that depends on the value of the data output signal. The restoring circuit includes a current mirror and a reference current source that generates a reference current in response to the data output signal.

Abstract: A phase locked delay circuit which reduces the layout area of a semiconductor device includes a delay buffer, a main delay portion, a delay line, means for detecting phase synchronization, a switching unit, a clock driver, and a flag signal generator. The delay buffer receives an external system clock signal, delays the received signal for a predetermined first delay time, and buffers the delayed signal. The main delay portion delays the output of the delay buffer for a predetermined second delay time in response to a flag signal, or bypasses the output of the delay buffer. The delay line sequentially delays the output of the main delay portion for a unit time. The phase synchronization detecting means detects a third delay time required for synchronizing the output of the main delay portion with the output of the delay buffer in response to the flag signal, using the output of the delay line, and activates a corresponding enable signal.