Abstract: A data input circuit for a semiconductor memory device uses an echo clock generator to reduce the clock cycle time. The echo clock is transmitted in the memory device with the data, thereby reducing the effects of clock skew and increasing the overall device operation speed. The circuit is particularly applicable to double data rate synchronous DRAM (DDR-SDRAM) circuitry.

Abstract: An internal clock generating circuit for data output buffers of a synchronous DRAM device, which produces an internal clock with reference to either the positive edge or the negative edge of the system clock CLK by comparing the reference time t.sub.CLref(OH) for insuring a low level time tCL of the system clock CLK and output hold time t.sub.OH, and which can sufficiently insure the data output setup time t.sub.OS and data output hold time t.sub.OH regardless of the frequency of the system clock by making the generation points of the internal clock to be varied depending on the frequency of the system clock.