Patents by Inventor Jung Ho Ahn

Jung Ho Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403818
    Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Kyu Yang, Seong Geon Park, Dong Jun Seong, Dong Ho Ahn, Jung Moo Lee, Seol Choi, Hideki Horii
  • Publication number: 20190267660
    Abstract: The present invention relates to a composition for a gel polymer electrolyte, a gel polymer electrolyte prepared by polymerizing the same, and a lithium secondary battery including the gel polymer electrolyte, and particularly, to a composition for a gel polymer electrolyte having improved high-temperature safety, a gel polymer electrolyte formed by polymerizing the composition in an inert atmosphere, and a lithium secondary battery including the gel polymer electrolyte.
    Type: Application
    Filed: January 12, 2018
    Publication date: August 29, 2019
    Applicant: LG Chem, Ltd.
    Inventors: Jung Hoon Lee, Kyoung Ho Ahn, Chul Haeng Lee, Jeong Woo Oh
  • Patent number: 10387014
    Abstract: A method and a mobile terminal for controlling the icons of the mobile terminal are provided. The method includes displaying at least one icon on a widget screen corresponding with a function for changing the size of the icon displayed on a touch screen; receiving a selection of an icon to which the function is to be applied; activating an attribute of the selected icon; and adjusting, if a side of the selected icon is dragged on the widget screen, a size of the selected icon according to a direction of the drag.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: August 20, 2019
    Assignees: Samsung Electronics Co., Ltd, Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: So-Young Kim, Yong-Gu Ji, Sung-Joo Ahn, Hwan Hwangbo, Hyo-Chang Kim, Jung-Hoon Park, Hyung-Jun Oh, Hyun-Guk Yoo, Gyeong-Ho Chu
  • Publication number: 20190234858
    Abstract: Provided is a method for evaluating fluid flow characteristics of a lens-free complementary metal-oxide semiconductor (CMOS) optical sensor package module with a flow channel. The method includes: measuring a propagation profile and a flow velocity in an initial state flow of a fluid in the flow channel; calculating a first statistical parameter relating to flow characteristics of the fluid from the measured propagation profile and flow velocity; and comparing the calculated first statistical parameter with a preset reference value and evaluating quality of the flow channel according to the comparison result.
    Type: Application
    Filed: September 29, 2017
    Publication date: August 1, 2019
    Inventors: Jong Muk LEE, Seong Won KWON, Ki Ho JANG, Jung Joon AHN, Tae Young LEE
  • Patent number: 10367024
    Abstract: A semiconductor device includes a light-receiving element which outputs electric charges in response to incident light, and a drive transistor which is gated by an output of the light-receiving element to generate a source-drain current in proportion to the incident light, wherein the drive transistor include a first gate electrode, a first channel region which is disposed under the first gate electrode, first source-drain regions which are disposed at respective ends of the first channel region and that have a first conductivity type, and a first channel stop region which is disposed on a side of the first channel region, and that separates the light-receiving element and the first channel region, the first channel stop region having a second conductivity type that is different from the first conductivity type.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungjoo Nah, Jung-Chak Ahn, Kyung-Ho Lee
  • Publication number: 20190226081
    Abstract: A method for manufacturing a thin metal layer assembly includes forming a thin metal layer including nanopatterns on a preliminary substrate. The method includes forming a metal reducing layer by chemically reducing the thin metal layer. The method includes separating the metal reducing layer from the preliminary substrate. The method includes bonding the metal reducing layer to a target substrate.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 25, 2019
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: JAE HO AHN, Jae Min Shin, Min Woo Kim, Won Sang Park, Sang Woo Kim, Jung Yong Lee
  • Publication number: 20190229316
    Abstract: Disclosed is an organic/inorganic composite porous film comprising: (a) inorganic particles; and (b) a binder polymer coating layer formed partially or totally on surfaces of the inorganic particles, wherein the inorganic particles are interconnected among themselves and are fixed by the binder polymer, and interstitial volumes among the inorganic particles form a micropore structure. A method for manufacturing the same film and an electrochemical device including the same film are also disclosed. An electrochemical device comprising the organic/inorganic composite porous film shows improved safety and quality.
    Type: Application
    Filed: April 3, 2019
    Publication date: July 25, 2019
    Applicants: LG Chem, Ltd., TORAY BATTERY SEPARATOR FILM CO., LTD.
    Inventors: Hyun Hang YONG, Sang Young LEE, Seok Koo KIM, Soon Ho AHN, Jung Don SUK
  • Publication number: 20190198925
    Abstract: The present invention relates to a non-aqueous electrolyte solution including a non-aqueous organic solvent, a lithium salt, and an oligomer represented by Formula 1 described in the present specification, and a lithium secondary battery including the same. Since the non-aqueous electrolyte solution according to an embodiment of the present invention may reduce gas, such as CO or CO2, generated in the secondary battery during high-temperature storage, it may further improve high-temperature stability of the lithium secondary battery.
    Type: Application
    Filed: January 12, 2018
    Publication date: June 27, 2019
    Applicant: LG Chem, Ltd.
    Inventors: Jung Hoon Lee, Kyoung Ho Ahn, Chul Haeng Lee, Jeong Woo Oh
  • Patent number: 10331366
    Abstract: A method of operating a data storage device configured to allow a plurality of non-volatile memory devices, including a first non-volatile memory device and second non-volatile memory devices, to lead control of power consumption. The method includes receiving, by each of the second non-volatile memory devices, a state signal indicating operation or non-operation of the first non-volatile memory device and determining, by each of the second non-volatile memory device, whether to operate based on the state signal.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Pil Lee, Seok Won Ahn, Hyun Ju Yi, Jun Ho Choi
  • Publication number: 20190189920
    Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.
    Type: Application
    Filed: February 15, 2019
    Publication date: June 20, 2019
    Inventors: Hideki Horii, Seong-Geon Park, Dong-Ho Ahn, Jung-Moo Lee
  • Patent number: 10318049
    Abstract: A touch screen panel disposed at the visible side of a display panel includes a sensing pattern formed on one visible side surface of a substrate, and a metal wiring disposed on a top side of a region corresponding to a boundary between pixels in the display panel on the above surface, which connects the sensing pattern with a pad part, thus exhibiting improved touch sensitivity and excellent transmittance.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: June 11, 2019
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Gi Hwan Ahn, Sung Ho Baek, Jung Ku Lim
  • Patent number: 10295705
    Abstract: Provided is an anti-reflection glass substrate comprising an anti-reflection layer having a predetermined thickness from the surface, the anti-reflection glass substrate being characterized in that the anti-reflection layer has at least two layers of a first layer and a second layer successively provided in the depth direction from the surface, each of the first layer and the second layer has a plurality of pores, and the porosity of the first layer is smaller than the porosity of the second layer. In addition, provided is a method for manufacturing an anti-reflection glass substrate, the method successively comprising a step of etching a glass substrate using a first etching liquid and a step of etching the glass substrate using a second etching liquid, the method being characterized in that the molarity of multivalent metal ions of the first etching liquid is larger than the molarity of multivalent metal ions of the second etching liquid.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: May 21, 2019
    Assignee: Corning Precision Materials Co., Ltd.
    Inventors: Jin Su Nam, Seon Ki Kim, Jung Keun Oh, Su Yeon Lee, Myeong Jin Ahn, Jae Ho Lee
  • Patent number: 10134487
    Abstract: A memory device may include a memory cell array, a bloom-filter circuit, a cache memory circuit, and a selecting circuit. The bloom-filter circuit may be configured to output a determination result signal that indicates that there is a possibility that a received address is one of failed addresses corresponding to failed cells of the memory cell array. The cache memory circuit may be configured to, store the failed addresses and a first set of data corresponding to the respective failed addresses, and configured to, when the determination result signal indicates a possibility, provide a comparison result signal by determining whether received address coincides with one of the failed addresses. The selecting circuit may be configured to output either first data of the first set of data or second data of the memory cell array corresponding to the received address based on determination result signal and comparison result signal.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 20, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SNU R&DB FOUNDATION
    Inventors: Sang-Hyuk Kwon, Young-Hoon Son, Jung-Ho Ahn
  • Patent number: 10096888
    Abstract: An electronic device is provided. The electronic device includes a front cover forming a front surface, a rear cover forming a rear surface, a sidewall at least partially enclosing a space formed between the front cover and the rear cover and at least partially formed of a conductive member, a display disposed in the space and including a screen region exposed through the front cover, a non-conductive structure disposed in adjacent to the sidewall or in contact with the sidewall in the space and including a first surface facing the front cover and a second surface facing the rear cover, a first antenna pattern overlapping the non-conductive structure and fed with electricity, a second antenna pattern overlapping the non-conductive structure and disposed adjacent to the first antenna pattern to form electromagnetic-field coupling with the first antenna pattern, and an integrated circuit chip feeding electricity to the first antenna pattern.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Ahn, Seung-Hwan Kim, Ho-Saeng Kim, Joon-Ho Byun
  • Publication number: 20180107406
    Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.
    Type: Application
    Filed: May 23, 2017
    Publication date: April 19, 2018
    Applicants: SNU R&DB FOUNDATION, WISCONSIN ALUMIN RESEARCH FOUNDATION
    Inventors: SEONG-IL O, Nam Sung KIM, Young-Hoon SON, Chan-Kyung KIM, Ho-Young SONG, Jung Ho AHN, Sang-Joon HWANG
  • Patent number: 9886340
    Abstract: A memory system and a method for the error correction of memory are disclosed herein. The method for the error correction of memory is performed by a memory system including a plurality of memory chips. The method for the error correction of memory may include reading, by a first ECC engine unit included in each of a plurality of memory chips, a chunk including a plurality of data bursts, first parity bits, and position bits from each of the plurality of memory chips; extracting, by the first ECC engine unit, a single data burst having an error from the plurality of data bursts using the position bits; and performing, by the first ECC engine unit, first error correction using the first parity bit corresponding to the extracted error data burst.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: February 6, 2018
    Assignees: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Jung Ho Ahn, Namsung Kim
  • Patent number: 9767887
    Abstract: A memory device includes a first memory cell, a second memory cell, a precharge circuit, a sense amplifier, a switch circuit, and a controller. The first memory cell is connected to a first bit line, the second memory cell is connected to a second bit line, and the precharge circuit connected between the first bit line and the second bit line. The sense amplifier includes a first input terminal and a second input terminal. The switch circuit is connected to the first bit line and the first input terminal and to the second bit line and the second input terminal and is configured to control a connection between the first bit line and the first input terminal and a connection between the second bit line and the second input terminal in response to a switch signal. The controller is configured to generate the switch signal in response to a command.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: September 19, 2017
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Young Hoon Son, Jung Ho Ahn, Seong Il O
  • Publication number: 20170091025
    Abstract: A memory system and a method for the error correction of memory are disclosed herein. The method for the error correction of memory is performed by a memory system including a plurality of memory chips. The method for the error correction of memory may include reading, by a first ECC engine unit included in each of a plurality of memory chips, a chunk including a plurality of data bursts, first parity bits, and position bits from each of the plurality of memory chips; extracting, by the first ECC engine unit, a single data burst having an error from the plurality of data bursts using the position bits; and performing, by the first ECC engine unit, first error correction using the first parity bit corresponding to the extracted error data burst.
    Type: Application
    Filed: March 2, 2016
    Publication date: March 30, 2017
    Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Jung Ho AHN, Namsung KIM
  • Publication number: 20160351998
    Abstract: An electronic device is provided.
    Type: Application
    Filed: May 12, 2016
    Publication date: December 1, 2016
    Inventors: Jung-Ho AHN, Seung-Hwan KIM, Ho-Saeng KIM, Joon-Ho BYUN
  • Publication number: 20160240242
    Abstract: A memory device includes a first memory cell, a second memory cell, a precharge circuit, a sense amplifier, a switch circuit, and a controller. The first memory cell is connected to a first bit line, the second memory cell is connected to a second bit line, and the precharge circuit connected between the first bit line and the second bit line. The sense amplifier includes a first input terminal and a second input terminal. The switch circuit is connected to the first bit line and the first input terminal and to the second bit line and the second input terminal and is configured to control a connection between the first bit line and the first input terminal and a connection between the second bit line and the second input terminal in response to a switch signal. The controller is configured to generate the switch signal in response to a command.
    Type: Application
    Filed: June 9, 2015
    Publication date: August 18, 2016
    Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Hoon SON, Jung Ho AHN, Seong Il O