Abstract: Methods and apparatus to determine and implement multidimensional network topologies are disclosed. An example method disclosed herein comprises receiving an input parameter for determining a multidimensional network topology for a network interconnecting a plurality of devices, and determining a set of multidimensional network topologies, each multidimensional network topology of the set comprising a respective plurality of nodes to interconnect the plurality of devices, each node in each multidimensional network topology of the set being fully connected with all neighbor nodes in each dimension of the multidimensional network topology, and each multidimensional network topology of the set satisfying a first constraint based on the input parameter.

Abstract: A circuit switched optical interconnection fabric includes a first hollow metal waveguide and a second hollow metal waveguide which intersects the first hollow metal waveguide to form an intersection. An optical element within the intersection is configured to selectively direct an optical signal between the first hollow metal waveguide and a second hollow metal waveguide.

Abstract: Various embodiments of the present invention relate to electronically tunable ring resonators. In one embodiment of the present invention, a resonator structure (300,1200) includes an inner resonator disposed on a surface of a substrate, and a phase-change layer (304,1204) covering the resonator. The resonance wavelength of the resonator structure can be selected by applying of a first voltage that changes the effective refractive index of the inner resonator and by applying of a second voltage that changes the effective refractive index of the phase-change layer.

Abstract: Methods and apparatus to determine and implement multidimensional network topologies are disclosed. An example method disclosed herein comprises receiving an input parameter for determining a multidimensional network topology for a network interconnecting a plurality of devices, and determining a set of multidimensional network topologies, each multidimensional network topology of the set comprising a respective plurality of nodes to interconnect the plurality of devices, each node in each multidimensional network topology of the set being fully connected with all neighbor nodes in each dimension of the multidimensional network topology, and each multidimensional network topology of the set satisfying a first constraint based on the input parameter.

Abstract: Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer pats are determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel.

Abstract: Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.

Abstract: A mobile terminal including a metal case and an antenna structure that can exhibit optimum radiation performance is provided. The antenna structure includes an antenna having a radiation unit for transmitting and for receiving electric waves, a Printed Circuit Board (PCB) to which the antenna is mechanically coupled at one surface thereof and having a power supply unit electrically coupled to the radiation unit, and a case constructed using a metal material within which the PCB is disposed, wherein the case has at least one slot formed in a surface thereof opposite to the surface to which the PCB is fastened and adjacent to the radiation unit.

Abstract: A synchronous optical bus system for communication between computer system components is described. In one example, the optical bus system is used for communication between a memory controller and memory devices optically coupled to an optical interconnect. Optical bus interface units couple the components to the optical interconnect and are arranged on the optical interconnect in order that a sum of an optical path length from a controller component to each computer system component and from each computer system component to the controller component is the same for all the coupled computer system components. A synchronous protocol is used for communication between the components.

Abstract: Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module (500) includes at least one virtual memory device and a demultiplexer register (502) disposed between the at least one virtual memory device and a memory controller. The demultiplexer register receives a command identifying one of the at least one virtual memory devices from the memory controller and sends the command to the identified virtual memory device. In addition, the at least one virtual memory devices include at least one memory chip.

Abstract: Various embodiments of the present invention are directed to methods that enable a memory controller to choose a particular operation mode for virtual memory devices of a memory module based on dynamic program behavior. In one embodiment, a method for determining an operation mode for each virtual memory device of a memory module includes selecting a metric (1001) that provides a standard by which performance and/or energy efficiency of the memory module is optimized during execution of one or more applications on a multicore processor. For each virtual memory device (1005), the method also includes collecting usage information (1006) associated with the virtual memory device over a period of time, determining an operation mode (1007) for the virtual memory device based on the metric and usage information, and entering the virtual memory device into the operation mode (1103, 1105, 1107, 1108).

Abstract: Illustrated is a computer system and method that includes a Processing Element (PE) to generate a data packet that is routed along a shortest path that includes a plurality of routers in a multiple dimension network. The system and method further include a router, of the plurality of routers, to de-route the data packet from the shortest path to an additional path, the de-route to occur where the shortest path is congested and the additional path links the router and an additional router in a dimension of the multiple dimension network.

Abstract: Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides.

Abstract: Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.

Abstract: Embodiments of the present invention relate to systems and methods for distributing an intentionally skewed optical-clock signal to nodes of a source synchronous computer system. In one system embodiment, a source synchronous system comprises a waveguide, an optical-system clock optically coupled to the waveguide, and a number of nodes optically coupled to the waveguide. The optical-system clock generates and injects a master optical-clock signal into the waveguide. The master optical-clock signal acquiring a skew as it passes between nodes. Each node extracts a portion of the master optical-clock signal and processes optical signals using the portion of the master optical-clock signal having a different skew for the respective extracting node.

Abstract: A multiband built-in antenna of a portable terminal is provided. The multiband built-in antenna includes a main board having a ground area and a non-ground area on a front surface and an opposite surface, and an antenna radiator having a specific pattern directly formed on the non-ground area of the main board, wherein the antenna radiator comprises a first antenna radiator of which one end is branched off into two parts on the front surface of the main board so that one part is used for feeding and the other part is electrically connected to the ground area, and of which the other end is extended by a specific length in a widthwise direction of the terminal, and a second antenna radiator which protrudes towards the opposite surface of the main board from the other end of the first antenna radiator and is formed in a specific pattern in the non-ground area on the opposite surface of the main board.

Abstract: A semiconductor device is disclosed. Embodiments relate to a semiconductor device which includes an active region including a source region, a drain region, and a channel region. A gate electrode, source electrodes, and a drain electrode are formed around the active region. A plurality of gate fingers diverge from the gate electrode into the channel region. A plurality of source fingers diverge from the source electrodes into the source region, the source fingers being disposed between the gate fingers in a predetermined pattern, the source fingers having at least two finger lines connected to each other via at least one grid line. A plurality of drain fingers diverge from the drain electrode into the drain region, the drain fingers being disposed between the gate fingers where the source fingers are not disposed.

Abstract: A semiconductor device including a semiconductor substrate having source/drain regions, a gate electrode formed on and/or over the semiconductor substrate, spacers formed against sidewalls of the gate electrode, an interlayer insulating layer formed over the semiconductor substrate and the gate electrode and having a plurality of contact holes formed therein, and contact plugs formed within the contact holes. The contact plugs can include a first contact plug and a second contact plug electrically connected to the gate electrode, and a third contact plug and a fourth contact plug electrically connected to the source/drain regions.

Abstract: A semiconductor device capacitor fabrication method that is capable of enabling the simultaneous use of an oxide capacitor and a PIP capacitor of a semiconductor device depending upon whether metal line terminals are used. The semiconductor device capacitor fabrication method can include forming an active region and a first gate electrode over a semiconductor substrate, partially depositing a silicon nitride layer, over which a capacitor will be formed, over the first gate electrode, forming a second gate electrode over the silicon nitride, sequentially forming a first insulation layer and a second insulation layer over the resultant structure and forming line terminals extending through the first insulating layer and the second insulating layer for a transistor and a capacitor.

Abstract: A mobile terminal including a metal case and an antenna structure that can exhibit optimum radiation performance is provided. The antenna structure includes an antenna having a radiation unit for transmitting and for receiving electric waves, a Printed Circuit Board (PCB) to which the antenna is mechanically coupled at one surface thereof and having a power supply unit electrically coupled to the radiation unit, and a case constructed using a metal material within which the PCB is disposed, wherein the case has at least one slot formed in a surface thereof opposite to the surface to which the PCB is fastened and adjacent to the radiation unit.

Abstract: Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.