Abstract: An optical system is provided and includes a first optical element driving mechanism, which includes a first fixed assembly, a first movable assembly, and a first driving assembly. The first movable assembly is configured to be connected to a first optical element, and the first movable assembly is movable relative to the first fixed assembly. The first movable assembly includes a first movable element and a second movable element. The first driving assembly is configured to drive the first movable assembly to move relative to the first fixed assembly. The first fixed assembly and the first movable assembly are arranged along a main axis, and the first driving assembly is configured to drive the second movable element to move along a first axis, thereby driving the first movable element to move around the main axis.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

Abstract: Disclosed is a delivery device, kit, system, method, etc. for localized fusion of leaflets of a tissue valve, for example, a native heart valve, using an adhesive. The delivery device can have one or more capture features for capturing separate leaflets, for example, the anterior and posterior mitral leaflets. An applicator can be configured to apply a biocompatible adhesive between the captured leaflets, and one or more curing elements can be configured to cure the applied biocompatible adhesive. The kit can have the aforementioned delivery device, and the biocompatible adhesive used therewith. The method can include positioning the aforementioned delivery device adjacent the anterior and posterior mitral leaflets, capturing the mitral leaflets between the paddles of the delivery device, applying a biocompatible adhesive between the captured mitral leaflets via the applicator, and curing the applied biocompatible adhesive via the energy elements to locally fuse the mitral leaflets.

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

Abstract: An electronic device with a receiving function is provided. The electronic device is adapted to receive and shift out an object. The electronic device includes a device housing, an actuating unit, a linkage unit and a holder. The actuating unit is disposed in the device housing. The linkage unit is connected to the actuating unit, wherein the actuating unit is adapted to move the linkage unit. The holder is connected to the device housing and the linkage unit, wherein the holder is adapted to be rotated between an extended orientation and a received orientation relative to the device housing, and the object is detachably connected to the holder.

Abstract: A stacked semiconductor device and systems and methods for producing the same are disclosed here. In some embodiments, the method includes aligning a first array of bond pads on an upper surface of a first semiconductor substrate with a second array of bond pads on a lower surface of a second semiconductor substrate. The method then includes annealing the stacked semiconductor device to bond the upper surface of the first semiconductor substrate to the lower surface of the second semiconductor substrate. The annealing results in at least one void between the upper surface and the lower surface that includes a layer of diffused metal. The layer of diffused metal extends from a first individual bond pad towards a second individual bond pad and forms an electrical or thermal short. The method then includes exposing the stacked semiconductor device to microwave radiation to excite a chemical constituent present in the void.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: A memory cell of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a first doped region, a second doped region, a gate structure, a protecting layer, a charge trapping layer, a dielectric layer, a first conducting line and a second conducting line. The first doped region and the second doped region are formed under a surface of the well region. The gate structure is formed over the surface of the well region. The protecting layer formed on the surface of the well region. The charge trapping layer covers the surface of the well region, the gate structure and the protecting layer. The dielectric layer covers the charge trapping layer. The first conducting line is connected with the first doped region. The second conducting line is connected with the second doped region.

Abstract: A method for performing automatic layout defect checking (ALDC) control regarding circuit design, associated apparatus and an associated computer-readable medium are provided. The method applicable to a processing circuit may include: providing a web-based entry in an ALDC control system running on a processing circuit, for any user among multiple users to upload at least a layout file of a package substrate design of at least one package substrate to the ALDC control system, in order to obtain at least the layout file from a client electronic device through the web-based entry; utilizing at least one backend program module to check the layout file according to a plurality of predetermined layout defect checking rules to generate at least one checking result, and create a layout defect checking report of the package substrate design; and sending the layout defect checking report corresponding to the layout file to the client electronic device.

Abstract: An optical component includes a substrate and a low reflection layer. The low reflection layer is disposed on a surface of the substrate, and the low reflection layer includes a plurality of nanoparticles. The nanoparticles are arranged in a stack configuration, and the number of the nanoparticles decreases progressively in a direction away from the substrate, such that an effective refractive index of the low reflection layer decreases progressively in the direction away from the substrate so as to prevent total reflection of light at the interface, thereby reducing reflectivity. When specific conditions are satisfied, the stacked nanoparticles can form a gradient-index film layer, and the low reflection layer can provide better anti-reflection capability.

Abstract: A plasticizer and a method for producing the same are provided. The method for producing the plasticizer includes: reacting a reaction mixture at each of a plurality of temperature holding stages in a heating process to form a semi-finished product; and purifying the semi-finished product at each of a plurality of low pressure stages of a decompression process to obtain a plasticizer. A temperature range of the heating process is from 140° C. to 220° C., a pressure range of the decompression process is from 750 Torr to 20 Torr, and the reaction mixture contains dibasic acid (e.g., adipic acid), diol (e.g. 1,4-butanediol), monohydric alcohol (e.g., 2-ethylhexanol), and catalyst (e.g., titanium catalyst).

Abstract: Provided is a lens module with an integrated structure, including a first lens and a second lens, a first substrate and a second substrate, an optical bonding layer, a first absorption layer and a second absorption layer, wherein the first absorption layer includes a copper complex, which is formed from a copper compound, a phosphonic acid represented by formula 1 herein, and at least one phosphorus-containing compound represented by formulas 2 to 4 herein. Due to the integrated structure, the lens module can be reduced in size. The manufacturing process is simplified because no assembly process is required. The lens module of the present disclosure exhibits high transmittance for visible light and low transmittance for near-infrared, showing an excellent near-infrared cut-off effect. In addition, while the incident light irradiates the lens module at different angles, the transmittance curve only is slightly shifted.

Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

Abstract: A non-volatile memory cell includes a select transistor and a memory transistor. The first drain/source terminal of the select transistor is connected with a first control terminal. The second drain/source terminal of the select transistor is connected with the first drain/source terminal of the memory transistor. The gate terminal of the select transistor is connected with a select gate terminal. The second drain/source terminal of the memory transistor is connected with a second control terminal. The gate terminal of the memory transistor is connected with a memory gate terminal. During a program action, the select transistor is turned on, and a tapered channel is formed in the memory transistor. The tapered channel is pinched off near the first drain/source terminal of the memory transistor, and plural hot carriers near a pinch off point are injected into the charge storage layer.

Abstract: A method of stabilizing performance of a processing device may include determining a maximum operational temperature of any number of cores of a processing device from a thermal control circuit of the processing device; setting a maximum power based on a maximum thermal capacity of the processing device to a power lower than the maximum operational temperature; increasing the power provided to the processing device when the maximum thermal capacity is below a set temperature; and placing the power provided to the processing device to an intermediate power level relative to the operational temperature and the maximum thermal capacity when operations of the processing device are to exceed the operational temperature of any of the cores of the processing device.