Patents by Inventor Jung Hsu

Jung Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12388026
    Abstract: An electronic package includes a base of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the base and rotated relative to the base above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the base.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: August 12, 2025
    Assignee: MEDIATEK INC.
    Inventors: Yao-Chun Su, Chih-Jung Hsu, Yi-Jou Lin, I-Hsuan Peng
  • Patent number: 12372776
    Abstract: An optical system includes a first optical element driving mechanism, including a first fixed assembly, a first movable assembly, and a first driving assembly. The first movable assembly is configured to be connected to at least two first optical elements. The first movable assembly includes a first movable element. The first driving assembly is configured to drive the first movable assembly to move relative to the first fixed assembly. The first fixed assembly and the first movable assembly are arranged along a main axis. The first driving assembly is configured to drive the first movable element to move around the main axis. A portion of the first driving assembly is disposed on the first movable element. When viewed in a direction perpendicular to the main axis, the first driving assembly exceeds the first fixed assembly and the first movable assembly.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: July 29, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chan-Jung Hsu, Chen-Hsin Huang, Chen-Hung Chao, Yi-Ho Chen, Kun-Shih Lin, Shou-Jen Liu
  • Patent number: 12374525
    Abstract: The method includes placing a wafer in a chamber body of a plasma processing tool; moving a first movable jig along an arc path to comb a spiral-shaped radio frequency (RF) coil over the chamber body, the first movable jig having a plurality of first confining slots penetrated by a plurality of coil segments of the spiral-shaped RF coil, respectively; and generating plasma in the chamber body through the spiral-shaped RF coil.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung Chang Huang, Chia Jung Hsu, Yu Hsiu Chen
  • Patent number: 12343841
    Abstract: A slurry blending tool may include a blending tank to receive and blend one or more materials into a slurry, and at least one inlet pipe connected to the blending tank and to provide the one or more materials to the blending tank. The at least one inlet pipe may vertically enter the blending tank and may not contact the blending tank. The slurry blending tool may include a blending pump partially provided within the blending tank and to blend the one or more materials into the slurry. The slurry blending tool may include an outlet pipe connected to the blending pump and to remove the slurry from the blending tank.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wei Chiu, Yung-Long Chen, Bo-Zhang Chen, Chong-Cheng Su, Yu-Chun Chen, Ching-Jung Hsu, Chi-Tung Lai
  • Publication number: 20250211251
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Application
    Filed: March 17, 2025
    Publication date: June 26, 2025
    Applicant: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 12341026
    Abstract: A chemical dispensing system is capable of simultaneously supplying a semiconductor processing chemical for production and testing through the use of independent chemical supply lines, which reduces production downtime of an associated semiconductor process, increases throughput and capability of the semiconductor process, and/or the like. Moreover, the capability to simultaneously supply the semiconductor processing chemical for production and testing allows for an increased quantity of semiconductor processing chemical batches to be tested with minimal impact to production, which increases quality control over the semiconductor processing chemical. In addition, the independent chemical supply lines may be used to supply the semiconductor processing chemical to production while independently filtering semiconductor processing chemical directly from a storage drum through a filtration loop.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chieh Hsu, Yung-Long Chen, Fang-Pin Chiang, Feng-An Yang, Ching-Jung Hsu, Chi-Tung Lai
  • Publication number: 20250194226
    Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.
    Type: Application
    Filed: February 23, 2025
    Publication date: June 12, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chun-Ya Chiu, Chia-Jung Hsu, Chin-Hung Chen
  • Patent number: 12287566
    Abstract: An optical system is provided and includes a first optical element driving mechanism, which includes a first fixed assembly, a first movable assembly, and a first driving assembly. The first movable assembly is configured to be connected to a first optical element, and the first movable assembly is movable relative to the first fixed assembly. The first movable assembly includes a first movable element and a second movable element. The first driving assembly is configured to drive the first movable assembly to move relative to the first fixed assembly. The first fixed assembly and the first movable assembly are arranged along a main axis, and the first driving assembly is configured to drive the second movable element to move along a first axis, thereby driving the first movable element to move around the main axis.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: April 29, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chan-Jung Hsu, Chen-Hsin Huang, Chen-Hung Chao, Yi-Ho Chen, Kun-Shih Lin, Shou-Jen Liu
  • Patent number: 12283971
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Grant
    Filed: January 15, 2024
    Date of Patent: April 22, 2025
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 12272693
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 8, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chia-Jung Hsu, Chin-Hung Chen
  • Publication number: 20250099090
    Abstract: Disclosed is a delivery device, kit, system, method, etc. for localized fusion of leaflets of a tissue valve, for example, a native heart valve, using an adhesive. The delivery device can have one or more capture features for capturing separate leaflets, for example, the anterior and posterior mitral leaflets. An applicator can be configured to apply a biocompatible adhesive between the captured leaflets, and one or more curing elements can be configured to cure the applied biocompatible adhesive. The kit can have the aforementioned delivery device, and the biocompatible adhesive used therewith. The method can include positioning the aforementioned delivery device adjacent the anterior and posterior mitral leaflets, capturing the mitral leaflets between the paddles of the delivery device, applying a biocompatible adhesive between the captured mitral leaflets via the applicator, and curing the applied biocompatible adhesive via the energy elements to locally fuse the mitral leaflets.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Inventors: Hengchu Cao, Shih-Hwa Shen, Holly Kung Jung Hsu, Krystal Ya-Fong Lai
  • Patent number: 12261086
    Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chun-Ya Chiu, Chia-Jung Hsu, Chin-Hung Chen
  • Patent number: 12253879
    Abstract: An electronic device with a receiving function is provided. The electronic device is adapted to receive and shift out an object. The electronic device includes a device housing, an actuating unit, a linkage unit and a holder. The actuating unit is disposed in the device housing. The linkage unit is connected to the actuating unit, wherein the actuating unit is adapted to move the linkage unit. The holder is connected to the device housing and the linkage unit, wherein the holder is adapted to be rotated between an extended orientation and a received orientation relative to the device housing, and the object is detachably connected to the holder.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: March 18, 2025
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chia-Jung Hsu, Shen-Pu Hsieh
  • Patent number: 12255645
    Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: March 18, 2025
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Jung Hsu, Chun-Yuan Lo, Chun-Hsiao Li, Chang-Chun Lung
  • Patent number: 12237299
    Abstract: A stacked semiconductor device and systems and methods for producing the same are disclosed here. In some embodiments, the method includes aligning a first array of bond pads on an upper surface of a first semiconductor substrate with a second array of bond pads on a lower surface of a second semiconductor substrate. The method then includes annealing the stacked semiconductor device to bond the upper surface of the first semiconductor substrate to the lower surface of the second semiconductor substrate. The annealing results in at least one void between the upper surface and the lower surface that includes a layer of diffused metal. The layer of diffused metal extends from a first individual bond pad towards a second individual bond pad and forms an electrical or thermal short. The method then includes exposing the stacked semiconductor device to microwave radiation to excite a chemical constituent present in the void.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: February 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Chia Jung Hsu, Eiichi Nakano
  • Publication number: 20250061022
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 20, 2025
    Applicant: Silicon Motion, Inc
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong DU
  • Patent number: 12216326
    Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: February 4, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Hsiang-Chin Lin, Shou-Jen Liu, Guan-Bo Wang, Kai-Po Fan, Chan-Jung Hsu, Shao-Chung Chang, Shih-Wei Hung, Ming-Chun Hsieh, Wei-Pin Chin, Sheng-Zong Chen, Yu-Huai Liao, Sin-Hong Lin, Wei-Jhe Shen, Tzu-Yu Chang, Kun-Shih Lin, Che-Hsiang Chiu, Sin-Jhong Song
  • Patent number: 12197285
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: January 14, 2025
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 12199160
    Abstract: A memory cell of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a first doped region, a second doped region, a gate structure, a protecting layer, a charge trapping layer, a dielectric layer, a first conducting line and a second conducting line. The first doped region and the second doped region are formed under a surface of the well region. The gate structure is formed over the surface of the well region. The protecting layer formed on the surface of the well region. The charge trapping layer covers the surface of the well region, the gate structure and the protecting layer. The dielectric layer covers the charge trapping layer. The first conducting line is connected with the first doped region. The second conducting line is connected with the second doped region.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: January 14, 2025
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chia-Jung Hsu, Wein-Town Sun
  • Patent number: D1063950
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 25, 2025
    Assignee: VIVOTEK INC.
    Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung