Abstract: A semiconductor device may include a single-photon avalanche diode (SPAD) arranged for illumination at a back surface of a substrate. The semiconductor device may include a full deep trench isolation (FDTI) structure between the SPAD and a neighboring SPAD of the semiconductor device. The FDTI may be associated with isolating the SPAD from the neighboring SPAD. The FDTI structure may include a shallow trench isolation (STI) element at the back surface of the substrate. The FDTI structure may include a deep trench isolation (DTI) element at a front surface of the substrate.

Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.

Abstract: A high voltage transistor structure including a substrate, a first drift region, a second drift region, a first cap layer, a second cap layer, a gate structure, a first source and drain region, and a second source and drain region is provided. The first and second drift regions are disposed in the substrate. The first and second cap layers are respectively disposed on the first and second drift regions. The gate structure is disposed on the substrate and located over at least a portion of the first drift region and at least a portion of the second drift region. The first and second source and drain regions are respectively disposed in the first and second drift regions and located on two sides of the gate structure. The size of the first drift region and the size of the second drift region are asymmetric.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: A stacked semiconductor device and systems and methods for producing the same are disclosed here. In some embodiments, the method includes aligning a first array of bond pads on an upper surface of a first semiconductor substrate with a second array of bond pads on a lower surface of a second semiconductor substrate. The method then includes annealing the stacked semiconductor device to bond the upper surface of the first semiconductor substrate to the lower surface of the second semiconductor substrate. The annealing results in at least one void between the upper surface and the lower surface that includes a layer of diffused metal. The layer of diffused metal extends from a first individual bond pad towards a second individual bond pad and forms and electrical or thermal short. The method then includes exposing the stacked semiconductor device to microwave radiation to excite a chemical constituent present in the void.

Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.

Abstract: The method includes placing a wafer in a chamber body of a plasma processing tool; moving a first movable jig along an arc path to comb a spiral-shaped radio frequency (RF) coil over the chamber body, the first movable jig having a plurality of first confining slots penetrated by a plurality of coil segments of the spiral-shaped RF coil, respectively; and generating plasma in the chamber body through the spiral-shaped RF coil.

Abstract: A memory device includes a well, a poly layer, a dielectric layer, an alignment layer and an active area. The poly layer is formed above the well. The dielectric layer is formed above the poly layer. The alignment layer is formed on the dielectric layer, used to receive an alignment layer voltage and substantially aligned with the dielectric layer in a projection direction. The active area is formed on the well. The dielectric layer is thicker than the alignment layer. A first overlap area of the poly layer and the active area is smaller than a second overlap area of the poly layer and the dielectric layer excluding the first overlap area.

Abstract: An adapter assembly and a projection device are provided. The projection device includes a device body, an illumination system, a light valve, the adapter assembly, and a projection lens. The light valve is disposed in the device body to convert the illuminating beam provided by the illumination system into an image beam. The projection lens includes a plurality of protruding claws that surround a circumferential surface of a main body and protrude along the radial direction. The adapter assembly includes a first ring member, a rotating plate, and a second ring member sequentially disposed along the axial direction of the adapter assembly. When the projection lens is assembled to the adapter assembly, the rotating plate rotates to limit the protruding claws within a limiting assembly space formed by the first ring member and the second ring member to lock the projection lens to the device body.

Abstract: A lithography system includes an extreme ultraviolet (EUV) light source, a reticle stage, a reflection layer, and a plurality of light permeable protrusions. The EUV light source is configured for generating an EUV light beam. The reticle stage is configured for holding a reticle with a front surface of the reticle facing in a downward direction. The reflection layer is below the reticle stage. The light permeable protrusions are formed on the reflection layer. Each of the light permeable protrusions includes a bouncing surface facing in a direction that forms an acute angle with the downward direction. A first portion of the EUV light beam from the EUV light source passes through the bouncing surface of each of the light permeable protrusions to the reflection layer and is reflected to the reticle by the reflection layer.

Abstract: A polymer, a quantum dot composition, and a light-emitting device employing the same are provided. The polymer includes a first repeat unit that has a structure represented by Formula (I): wherein the definitions of R1, R2, A1, A2, A3, and Z1 and n are as defined in the specification.

Abstract: A module comprises a display element, a first polarizing element, a light sensor, a transparent layer, and a second polarizing element. The display element emits a display light source. The first polarizing element covers the display element, and blocks a first phase portion of the display light source and allows a second phase portion of the display light source to penetrate. The transparent layer covers the first polarizing element. The light sensor is disposed on one side of the display element or the first polarizing element. The second polarizing element is disposed between the light sensor and the transparent layer and blocks a second phase portion of the display light source.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first component in a substrate. The semiconductor arrangement includes a gap fill layer. A first portion of the gap fill layer overlies the first component. The first portion of the gap fill layer has a tapered sidewall. A first portion of the substrate separates the first portion of the gap fill layer from the first component.

Abstract: A memory cell of a memory cell array includes a well region, a first doped region, a second doped region, a first gate structure, and a storage structure. The first doped region and the second doped region are formed in the well region. The first gate structure is formed over a first surface between the first doped region and the second doped region. The storage structure is formed over a second surface and the second surface is between the first surface and the second doped region. The storage structure is covered on a portion of the first gate structure, the second surface and an isolation structure.

Abstract: A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.

Abstract: Organic metal compounds and organic light-emitting devices employing the same are provided. The organic metal compound has a chemical structure of Formula (I) or Formula (II): In particular, one of the following two conditions (1) and (2) is met: (1) R1 is deuterium or C1-6 deuterated alkyl group, when R3 and R4 are independently hydrogen, halogen, C1-6 alkyl group, C1-6 fluoroalkyl or C3-12 heteroaryl group; and (2) R1 is hydrogen, deuterium, C1-6 alkyl group, C1-6 deuterated alkyl group, C3-12 heteroaryl group, or C6-12 aryl group, when at least one of R3 and R4 is C6-12 aryl group or C6-12 fluoroaryl group.

Abstract: A memory device includes a first well, a second well, a first active area, a second active area, a third active area, a first poly layer and a second poly layer. The first well is of a first conductivity type. The second well is of a second conductivity type different from the first conductivity type. The first active area is of the second conductivity type and is formed on the first well. The second active area is of the first conductivity type and is formed on the first well and between the first active area and the second well. The third active area is of the first conductivity type and is formed on the second well. The first poly layer is formed above the first well and the second well. The second poly layer is formed above the first well.

Abstract: A clamping device includes first and second clamping components and at least one elastic component. The first clamping component includes a first clamping portion and two first pivot portions connected to the first clamping portion. The second clamping component includes a second clamping portion and two second pivot portions connected to the second clamping portion. The second pivot portions are pivotally connected to the first pivot portions respectively, such that the first and second clamping components are capable of rotating relative to each other to present a first state and a second state. The elastic component is connected to the first clamping component and the second clamping component. When the first and second clamping components are in the second state, the elastic component provides an elastic force for the first clamping portion and the second clamping portion to be restored to the first state to clamp an object.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.