Patents by Inventor Jung-Hsuan Chen

Jung-Hsuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915666
    Abstract: A display device, a display driving integrated circuit (DDIC), and an operation method are provided. The display device includes a display panel, a first DDIC, and a second DDIC. The first DDIC generates a display synchronization signal, and drives a first display area of a display panel according to the display synchronization signal. The second DDIC is coupled to the first DDIC to receive the display synchronization signal. The second DDIC performs a frequency tracking operation on an internal clock signal of the second DDIC by selectively using the display synchronization signal. The second DDIC drives a second display area of the display panel according to the internal clock signal and the display synchronization signal.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 27, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Jung-Hsuan Sung, Kai-Wen Shao, Chien-Yu Chen
  • Publication number: 20240021613
    Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second transistor disposed over the first transistor, and a conductive trace. The first transistor includes first conductive segments, corresponding to drain and source terminals of the first transistor and extending in a first direction, on a first layer. The second transistor includes second conductive segments, corresponding to drain and source terminals of the second transistor and extending in the first direction, on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in the first direction, and the third layer is interposed between the first and second layers. The first conductive segments, the second conductive segments, and the conductive trace overlap in a layout view.
    Type: Application
    Filed: July 31, 2023
    Publication date: January 18, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pin-Dai SUE, Tzung-Yo HUNG, Jung-Hsuan CHEN, Ting-Wei CHIANG
  • Patent number: 11798940
    Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second disposed over the first transistor, and a conductive trace. The first transistor includes a first active area extending on a first layer. The second transistor includes a second active area extending on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in a first direction, and the third layer is interposed between the first and second layers. The first active area, the second active area, and the conductive trace overlap in a layout view.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pin-Dai Sue, Tzung-Yo Hung, Jung-Hsuan Chen, Ting-Wei Chiang
  • Publication number: 20230124337
    Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
  • Publication number: 20230111939
    Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 13, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
  • Patent number: 11552085
    Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Cheng Xiao, Jhih-Siang Hu, Ru-Yu Wang, Jung-Hsuan Chen, Ting-Wei Chiang
  • Publication number: 20220384644
    Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.
    Type: Application
    Filed: July 25, 2022
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ze-Sian Lu, Ting-Wei Chiang, Pin-Dai Sue, Jung-Hsuan Chen, Hui-Wen Li
  • Patent number: 11469321
    Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ze-Sian Lu, Ting-Wei Chiang, Pin-Dai Sue, Jung-Hsuan Chen, Hui-Wen Li
  • Publication number: 20220102363
    Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
  • Patent number: 11238905
    Abstract: A sense amplifier (SA) includes a semiconductor substrate having a source/drain (S/D) diffusion region; a pair of SA sensing devices both disposed in the S/D diffusion region; an SA enabling device disposed in the same S/D diffusion region as where the pair of SA sensing devices are disposed in; and a sense amplifier enabling signal (SAE) line for carrying an SAE signal, for turning on the SA enabling device to discharge one of the pair of SA sensing devices during a data read from the sense amplifier, wherein the SA enabling device is arranged to provide buffer protection for source/drain terminals of the pair of SA sensing devices.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Huei Chen, Chien Chi Linus Tien, Kao-Cheng Lin, Jung-Hsuan Chen
  • Patent number: 11143161
    Abstract: A wind power generation device includes a wind blocking structure, which is in a box-shaped structure fixed on ground by a bottom plane thereof; a wind vane rotating body including a rotating shaft and vanes fixed on the rotating shaft and arranged at equal angle intervals, wherein the rotating shaft is mounted on two bearings of the wind blocking structure, and the vanes are rotatable inside the box-shaped structure; a power generator connected to the rotating shaft and fixed on the box-shaped structure by a linking plate. When wind blows to the wind blocking structure to rotate the wind vane rotating body, the power generator is driven by the rotating shaft to generate electrical power. The wind power generation device can include at least two wind vane rotating bodies, or area enlarging structures added on the vanes, to increase windward areas of the vanes.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 12, 2021
    Assignee: NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chin-Guo Kuo, Jung-Hsuan Chen, Chao-Fu Shu, Ya-Chiao Liu
  • Publication number: 20210273093
    Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: Ze-Sian Lu, Ting-Wei Chiang, Pin-Dai Sue, Jung-Hsuan Chen, Hui-Wen Li
  • Patent number: 10991423
    Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
  • Patent number: 10964230
    Abstract: A computing appliance for geometric planimetry is provided, comprising a container, a vertical dividing rule, a horizontal dividing rule, a horizontal point line and a middle point line. A fluid is filled into the container, and the vertical dividing rule, the horizontal dividing rule, the horizontal point line and the middle point line are configured on a same instructing surface of the container and arranged on each of the periphery surrounding like a rectangle. When the container is vertically disposed, a fluid level is aligned with the horizontal point line. And, when the container is tilted to form at least one angle, an area of at least one geometric shape can be derived by employing the vertical dividing rule, the horizontal dividing rule, the horizontal point line and the middle point line.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: March 30, 2021
    Assignee: National Taiwan Normal University
    Inventors: Chin-Guo Kuo, Jung-Hsuan Chen, Chao-Fu Shu
  • Publication number: 20210047994
    Abstract: A wind power generation device includes a wind blocking structure, which is in a box-shaped structure fixed on ground by a bottom plane thereof; a wind vane rotating body including a rotating shaft and vanes fixed on the rotating shaft and arranged at equal angle intervals, wherein the rotating shaft is mounted on two bearings of the wind blocking structure, and the vanes are rotatable inside the box-shaped structure; a power generator connected to the rotating shaft and fixed on the box-shaped structure by a linking plate. When wind blows to the wind blocking structure to rotate the wind vane rotating body, the power generator is driven by the rotating shaft to generate electrical power. The wind power generation device can include at least two wind vane rotating bodies, or area enlarging structures added on the vanes, to increase windward areas of the vanes.
    Type: Application
    Filed: September 16, 2019
    Publication date: February 18, 2021
    Inventors: Chin-Guo KUO, Jung-Hsuan CHEN, Chao-Fu SHU, Ya-Chiao LIU
  • Patent number: 10906781
    Abstract: A pneumatic vertical transportation device comprises an expandable cylinder, a carriage rack, an air piping controller, and an air exhauster. The expandable cylinder includes a bellow body, with one end hanging carriage rack and the other end connected with a fixing plate. The expandable cylinder is connected with the air piping controller. While the carriage rack is rising, the air exhauster draws air from the bellow body through the air piping controller to gradually decrease pressure inside. Once pressure difference exceeds weight of the carriage rack, the carriage rack begins to rise. Volume of the expandable cylinder is reduced such that the lower disc of the expandable cylinder approaches top, and the expandable cylinder is maintained at low pressure state. While the carriage rack is descending, air is fed into the expandable cylinder through the air piping controller to gradually expand the bellow body, letting the carriage rack descend.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 2, 2021
    Assignee: National Taiwan Normal University
    Inventors: Jung-Hsuan Chen, Chin-Guo Kuo, Chao-Fu Shu
  • Patent number: 10900464
    Abstract: A method of automatically extracting energy from flowing liquid and a device using the same are disclosed. The device includes a paddle rod and a swing device. The paddle rod includes two paddles to bear a pushing force of flowing liquid. When the paddle rod is swung, one of the two paddle enters water and the other paddle leaves from water surface. When the paddle in the water bears a pushing force of flowing liquid to drive a rotary body to swing, the paddle rod moves upwardly and leaves the water surface, and the other paddle enters water to bear the pushing force, and after the rotary body is driven to swing reversely, the paddle rod moves upwardly and leaves water surface, and at the same time the paddle enters the water to bear the pushing force, to drive the rotary body to swing reversely.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: January 26, 2021
    Assignee: National Taiwan Normal University
    Inventors: Chin-Guo Kuo, Jung-Hsuan Chen, Chao-Fu Shu
  • Patent number: 10895251
    Abstract: A device for accumulating atmospheric pressure includes a supporting device, at least two expandable chambers, a five-opening air valve, and an exhauster. The expandable chambers are installed on the supporting device. The number of the expandable chambers is an even number. The expandable chambers are uniformly arranged at two opposite sides of the supporting device. The five-opening air valve is connected with the expandable chambers to communicate with the internal spaces of the at least two expandable chambers, and receives atmospheric pressure. The exhauster connects and communicates with the five-opening air valve. According to the switching state of the five-opening air valve, the exhauster exhausts the internal space of one of the expandable chambers through the five-opening air valve or the atmospheric pressure inflates the internal space of one of the expandable chambers through the five-opening air valve, thereby driving the supporting device.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: January 19, 2021
    Assignee: NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chin-Guo Kuo, Jung-Hsuan Chen, Chao-Fu Shu
  • Publication number: 20210010454
    Abstract: A method of automatically extracting energy from flowing liquid and a device using the same are disclosed. The device includes a paddle rod and a swing device. The paddle rod includes two paddles to bear a pushing force of flowing liquid. When the paddle rod is swung, one of the two paddle enters water and the other paddle leaves from water surface. When the paddle in the water bears a pushing force of flowing liquid to drive a rotary body to swing, the paddle rod moves upwardly and leaves the water surface, and the other paddle enters water to bear the pushing force, and after the rotary body is driven to swing reversely, the paddle rod moves upwardly and leaves water surface, and at the same time the paddle enters the water to bear the pushing force, to drive the rotary body to swing reversely.
    Type: Application
    Filed: July 31, 2019
    Publication date: January 14, 2021
    Inventors: Chin-Guo KUO, Jung-Hsuan CHEN, Chao-Fu SHU
  • Publication number: 20200411516
    Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second disposed over the first transistor, and a conductive trace. The first transistor includes a first active area extending on a first layer. The second transistor includes a second active area extending on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in a first direction, and the third layer is interposed between the first and second layers. The first active area, the second active area, and the conductive trace overlap in a layout view.
    Type: Application
    Filed: June 9, 2020
    Publication date: December 31, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pin-Dai SUE, Tzung-Yo HUNG, Jung-Hsuan CHEN, Ting-Wei CHIANG