Patents by Inventor Jung-Hsuan Chen
Jung-Hsuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8928113Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.Type: GrantFiled: April 8, 2011Date of Patent: January 6, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Yu Pan, Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen, Hung-Jen Liao
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Patent number: 8837250Abstract: A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.Type: GrantFiled: July 20, 2010Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: You-Cheng Xiao, Hong-Chen Cheng, Chung-Ji Lu, Cheng Hung Lee, Jung-Hsuan Chen, Li-Chun Tien
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Patent number: 8816403Abstract: Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.Type: GrantFiled: September 21, 2011Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jung-Hsuan Chen, May Chang, Chiting Cheng, Li-Chun Tien
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Patent number: 8692333Abstract: A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.Type: GrantFiled: August 12, 2010Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Huei Chen, You-Cheng Xiao, Jung-Hsuan Chen, Shao-Yu Chou
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Publication number: 20140073124Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.Type: ApplicationFiled: November 14, 2013Publication date: March 13, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Huei CHEN, Jung-Hsuan CHEN, Shao-Yu CHOU, Hung-Jen LIAO, Li-Chun TIEN
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Patent number: 8665654Abstract: A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.Type: GrantFiled: June 21, 2013Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Chen Cheng, Ming-Yi Lee, Kuo-Hua Pan, Jung-Hsuan Chen, Li-Chun Tien, Cheng Hung Lee, Hung-Jen Liao
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Patent number: 8610236Abstract: A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.Type: GrantFiled: August 6, 2010Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Hung-Jen Liao, Li-Chun Tien
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Publication number: 20130286708Abstract: A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.Type: ApplicationFiled: June 21, 2013Publication date: October 31, 2013Inventors: Hong-Chen CHENG, Ming-Yi LEE, Kuo-Hua PAN, Jung-Hsuan CHEN, Li-Chun TIEN, Cheng Hung LEE, Hung-Jen LIAO
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Patent number: 8482990Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.Type: GrantFiled: February 11, 2011Date of Patent: July 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Chen Cheng, Ming-Yi Lee, Kuo-Hua Pan, Jung-Hsuan Chen, Li-Chun Tien, Cheng Hung Lee, Hung-Jen Liao
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Patent number: 8455354Abstract: A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.Type: GrantFiled: April 6, 2011Date of Patent: June 4, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hsuan Chen, Yen-Huei Chen, Li-Chun Tien, Hung-Jen Liao
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Publication number: 20130121055Abstract: A word line driver cell suitable for RAM devices such as SRAM, static random access memory devices, is provided. The word line driver cell is compatible with double pattern processing techniques and enables the formation of all word lines from a single metal layer which, in turn, enables overlying and underlying metal levels to be used for other features such as signal lines for word line decoders. A power mesh is formed using multiple metal layers and the formation of all the word lines from a single metal layer enables VDD and VSS power lines that are formed from an overlying layer to extend orthogonal to the cell direction and include wider widths reducing metal line resistance and increasing the deliverable power.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu Cheng HUANG, Hsin-Hsin KO, Jung-Hsuan CHEN, Chiting CHENG
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Patent number: 8437166Abstract: A word line driver cell suitable for RAM devices such as SRAM, static random access memory devices, is provided. The word line driver cell is compatible with double pattern processing techniques and enables the formation of all word lines from a single metal layer which, in turn, enables overlying and underlying metal levels to be used for other features such as signal lines for word line decoders. A power mesh is formed using multiple metal layers and the formation of all the word lines from a single metal layer enables VDD and VSS power lines that are formed from an overlying layer to extend orthogonal to the cell direction and include wider widths reducing metal line resistance and increasing the deliverable power.Type: GrantFiled: November 16, 2011Date of Patent: May 7, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu Cheng Huang, Hsin-Hsin Ko, Jung-Hsuan Chen, Chiting Cheng
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Publication number: 20130069236Abstract: Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.Type: ApplicationFiled: September 21, 2011Publication date: March 21, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jung-Hsuan Chen, May Chang, Chiting Cheng, Li-Chun Tien
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Publication number: 20120256235Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.Type: ApplicationFiled: April 8, 2011Publication date: October 11, 2012Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Yu Pan, Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen, Hung-Jen Liao
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Publication number: 20120258592Abstract: A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.Type: ApplicationFiled: April 6, 2011Publication date: October 11, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hsuan Chen, Yen-Huei Chen, Li-Chun Tien, Hung-Jen Liao
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Publication number: 20120206953Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.Type: ApplicationFiled: February 11, 2011Publication date: August 16, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hong-Chen CHENG, Ming-Yi LEE, Kuo-Hua PAN, Jung-Hsuan CHEN, Li-Chun TIEN, Cheng Hung LEE, Hung-Jen LIAO
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Publication number: 20120181707Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao
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Publication number: 20120037997Abstract: A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.Type: ApplicationFiled: August 12, 2010Publication date: February 16, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Huei CHEN, You-Cheng XIAO, Jung-Hsuan CHEN, Shao-Yu CHOU
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Publication number: 20120032293Abstract: A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.Type: ApplicationFiled: August 6, 2010Publication date: February 9, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Huei CHEN, Jung-Hsuan CHEN, Shao-Yu CHOU, Hung-Jen LIAO, Li-Chun TIEN
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Publication number: 20120020179Abstract: A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.Type: ApplicationFiled: July 20, 2010Publication date: January 26, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACURING CO., LTD.Inventors: You-Cheng XIAO, Hong-Chen CHENG, Chung-Ji LU, Cheng Hung LEE, Jung-Hsuan CHEN, Li-Chun TIEN