Patents by Inventor Jung-Hsuan Chen
Jung-Hsuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10107664Abstract: A measurement tool for circle area includes a cylinder, a rectangular container and a pipe. The cylinder is provided with a first opening and filled with a liquid. The rectangular container is provided with a second opening, and at least side surface of the rectangular container is provided with at least scale table. The pipe is arranged on the cylinder and the rectangular container and connected with the first opening and the second opening. When the cylinder is tilted, the liquid flows to the rectangular container through the pipe, and a volume of the liquid in the rectangular container is figured out according to a length, a width and a height of the rectangular container and the scale table. The volume equals an inner-cylinder volume of the cylinder. An inner-circle area of the cylinder is obtained according to the inner-cylinder volume and a height of the cylinder.Type: GrantFiled: March 3, 2017Date of Patent: October 23, 2018Assignee: NATIONAL TAIWAN NORMAL UNIVERSITYInventors: Jung-Hsuan Chen, Chin-Guo Kuo, Chao-Fu Shu
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Patent number: 10032490Abstract: A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.Type: GrantFiled: October 10, 2016Date of Patent: July 24, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Huei Chen, Chien Chi Linus Tien, Kao-Cheng Lin, Jung-Hsuan Chen
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Publication number: 20180188012Abstract: A measurement tool for circumference includes at least one disk with a circumference thereof provided with a through hole; a straightedge provided with a fixed post and a plurality of scales, and the fixed post penetrates through the through hole to fix the disk to the fixed post; and a hitching line with one end thereof penetrated by the fixed post, and the other end of the hitching line surrounds the disk or straightens along the straightedge. Thus, a string makes a circle around the circumference, whereby the string is marked an index corresponding to the fixed post, and then the string straightens along the straightedge, and a length of the circumference of the disk is obtained according to relative positions of the scales and the index.Type: ApplicationFiled: March 3, 2017Publication date: July 5, 2018Inventors: Jung-Hsuan Chen, Chin-Guo Kuo, Chao-Fu Shu
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Publication number: 20180172497Abstract: A measurement tool for circle area includes a cylinder, a rectangular container and a pipe. The cylinder is provided with a first opening and filled with a liquid. The rectangular container is provided with a second opening, and at least side surface of the rectangular container is provided with at least scale table. The pipe is arranged on the cylinder and the rectangular container and connected with the first opening and the second opening. When the cylinder is tilted, the liquid flows to the rectangular container through the pipe, and a volume of the liquid in the rectangular container is figured out according to a length, a width and a height of the rectangular container and the scale table. The volume equals an inner-cylinder volume of the cylinder. An inner-circle area of the cylinder is obtained according to the inner-cylinder volume and a height of the cylinder.Type: ApplicationFiled: March 3, 2017Publication date: June 21, 2018Inventors: Jung-Hsuan Chen, Chin-Guo Kuo, Chao-Fu Shu
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Publication number: 20180137910Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: ApplicationFiled: January 15, 2018Publication date: May 17, 2018Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Patent number: 9928899Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: GrantFiled: December 22, 2016Date of Patent: March 27, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Patent number: 9853035Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.Type: GrantFiled: January 5, 2015Date of Patent: December 26, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Yu Pan, Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen, Hung-Jen Liao
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Publication number: 20170186483Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: ApplicationFiled: December 22, 2016Publication date: June 29, 2017Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Patent number: 9589885Abstract: An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.Type: GrantFiled: August 26, 2015Date of Patent: March 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Jen Liao, Jung-Hsuan Chen, Chien Chi Tien, Ching-Wei Wu, Jui-Che Tsai, Hong-Chen Cheng, Chung-Hsing Wang
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Publication number: 20170032827Abstract: A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.Type: ApplicationFiled: October 10, 2016Publication date: February 2, 2017Inventors: Yen-Huei CHEN, Chien Chi Linus TIEN, Kao-Cheng LIN, Jung-Hsuan CHEN
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Patent number: 9466493Abstract: A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.Type: GrantFiled: July 11, 2013Date of Patent: October 11, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Huei Chen, Chien Chi Tien, Kao-Cheng Lin, Jung-Hsuan Chen
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Patent number: 9425095Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.Type: GrantFiled: May 24, 2015Date of Patent: August 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao
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Publication number: 20150364412Abstract: An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.Type: ApplicationFiled: August 26, 2015Publication date: December 17, 2015Inventors: Hung-Jen LIAO, Jung-Hsuan CHEN, Chien Chi TIEN, Ching-Wei WU, Jui-Che TSAI, Hong-Chen CHENG, Chung-Hsing WANG
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Publication number: 20150255338Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.Type: ApplicationFiled: May 24, 2015Publication date: September 10, 2015Inventors: You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao
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Patent number: 9129956Abstract: An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer.Type: GrantFiled: December 11, 2013Date of Patent: September 8, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Jen Liao, Jung-Hsuan Chen, Chien Chi Tien, Ching-Wei Wu, Jui-Che Tsai, Hong-Chen Cheng, Chung-Hsing Wang
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Patent number: 9064799Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.Type: GrantFiled: November 14, 2013Date of Patent: June 23, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Hung-Jen Liao, Li-Chun Tien
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Publication number: 20150162273Abstract: An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer.Type: ApplicationFiled: December 11, 2013Publication date: June 11, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Jen LIAO, Jung-Hsuan CHEN, Chien Chi TIEN, Ching-Wei WU, Jui-Che TSAI, Hong-Chen CHENG, Chung-Hsing WANG
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Patent number: 9041069Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.Type: GrantFiled: January 14, 2011Date of Patent: May 26, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao
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Publication number: 20150118803Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.Type: ApplicationFiled: January 5, 2015Publication date: April 30, 2015Inventors: Hsien-Yu PAN, Jung-Hsuan CHEN, Shao-Yu CHOU, Yen-Huei CHEN, Hung-Jen LIAO
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Publication number: 20150015335Abstract: A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.Type: ApplicationFiled: July 11, 2013Publication date: January 15, 2015Inventors: Yen-Huei CHEN, Chien Chi TIEN, Kao-Cheng LIN, Jung-Hsuan CHEN