Abstract: Disclosed herein are a portable terminal and method. The portable terminal includes a display module and at least one processor operatively coupled to the memory, which may implemented the method to control the display module to display a first image operable to indicate a state of a user, and in response to receiving response information while the first image is displayed, determine a state of the user according to the received response information.

Abstract: A spatial image having 2D spatial information is obtained from a surface of a sample by an image creating method. The surface of the sample is milled to obtain an elemental image having material information from the milled surface. The spatial image and the elemental image are composed to form a 2D spatial/elemental image.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.

Abstract: Provided are an initiator and a method for debonding a wafer supporting system. The initiator for debonding a wafer supporting system includes a rotation chuck having an upper surface on which a wafer supporting system (WSS), which includes a carrier wafer, a device wafer, and a glue layer for bonding the carrier wafer and the device wafer to each other, is seated to rotate the wafer supporting system, a detecting module detecting a height and a thickness of the glue layer and a laser module generating a fracture portion on the glue layer through irradiating a side surface of the glue layer with a laser on the basis of the height and the thickness of the glue layer.

Abstract: A method of manufacturing a filter pipe for vehicles which has an expanded tube portion with a different diameter at one side and is provided with a plurality of through holes formed along a circumferential direction includes: forming the plurality of through holes in a mother member; forming furrows at one end portion of the mother member; forming a planar member having the plurality of through holes and the furrows by a shearing process of the mother member; bending the planar member in a tubular shape and spreading the furrows to form an area where the furrows are formed in an expanded tube shape; and adhering both facing end portions of the planar member so as to form a body having the expanded tube portion at one side thereof.

Abstract: A semiconductor inspection system including an ion beam milling unit configured to irradiate at least one cluster-ion beam onto a surface of a sample wafer and etch the surface of the sample wafer and an image acquisition unit configured to irradiate an electron beam onto the etched surface of the sample wafer and acquire an image of the etched surface may be provided.

Abstract: A retainer for a wafer carrier comprising: a body including a plurality of slots configured to receive side surfaces of wafers; and for each of the slots, a supporting structure formed on a sidewall of the slot and configured to make contact with the side surfaces of a corresponding wafer, the supporting structure being spaced apart from an upper corner of the side surface of the corresponding wafer.

Abstract: The present invention relates to a camera module, the camera module including a PCB (Printed Circuit Board) mounted with an image sensor, a base formed with an IRCF (Infrared Cut Filter) at a position corresponding to that of the image sensor, a bobbin including a coil winding unit vertically reciprocatively formed at an upper surface of the base and provided at a periphery, and a plurality of rib members protrusively formed from a floor surface, a yoke formed with a magnet arranged at a position corresponding to that of a coil of the bobbin, and a shock absorption member arranged at an ambience of the rib members and longer than the rib member, wherein the shock absorption member is compressed by being elastically deformed, in a case the base is brought into contact with the rib member.

Abstract: A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer.

Abstract: Disclosed herein is a battery pack including a battery cell having a first electrode terminal and a second electrode terminal, a protection circuit module (PCM) including a protection circuit board (PCB), at which a safety element is mounted, the PCB having a protection circuit, and connection members (A and B) connected respectively to the first and second electrode terminals of the battery cell, an electrically insulative pack frame configured to have a structure in which the battery cell is mounted in the pack frame, the pack frame having an insulative mounting part, at a top of which the PCB is mounted, an electrically insulative top cap mounted at a top of the battery cell while surrounding the PCM, an electromagnetic induction type charging coil mounted at at least one main surface of the battery cell, the charging coil being connected to the PCM, and a shielding member interposed between the battery cell and the charging coil.

Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.

Abstract: Disclosed herein is a top cap assembly mounted to a battery cell having an electrode assembly of a cathode/separator/anode structure disposed in a battery case together with an electrolyte in a sealed state, the battery case being provided at an upper end thereof with a first electrode terminal and a second electrode terminal, the top cap assembly including a protection circuit module (PCM) and an electrically insulative top cap housing mounted to the upper end of the battery cell while surrounding an outside of the PCM, wherein the PCM includes a protection circuit board (PCB) having a protection circuit formed thereon, the PCB being coupled to a mechanical coupling part of a terminal block, connecting parts connected to the first electrode terminal and the second electrode terminal, a safety element, and the terminal block mounted to the PCM, the terminal block including connectors.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.