Abstract: Methods, systems, and. devices may assist in new radio (NR) sidelink (SL) operation in licensed or unlicensed spectrum. In an example, if listen-before-talk (LBT) failure rate is low, then implicit acknowledgement (ACK) and explicit non-acknowledgement (NACK) may be used. A first SL timer may start when a. SL transport block is transmitted. If no explicit NACK, is received before the SL timer expires, then ACK. may be assumed. If LBT failure rate is high, then explicit ACK and implicit NACK may be used. A second SL timer may start. If no explicit ACK is received before the SL timer expires, then NACK may be assumed.

Abstract: The present invention relates to an on-board redundant controller and standby aviation sensors in-flight reconfigurable autonomous flight system, which includes UAV, primary autopilot module, secondary autopilot module and switching module. The primary autopilot module and secondary autopilot module are equipped with first aviation sensing module and second aviation sensing module. The primary autopilot module produces response signal according to the request signal produced by the secondary autopilot module. When the first response signal is no longer produced by the primary autopilot module for a preset time, the first switching module switches controls of the flight control module from the primary autopilot module to the secondary autopilot module, and the secondary autopilot module uses the aviation data of the second aviation sensing module to provide flight control signals to the flight control module.

Abstract: An integrated circuit device includes a first metallization layer, a second metallization layer, and a first metal via. The first metallization layer comprises two adjacent first metal lines. The second metallization layer is over the first metallization layer, wherein the second metallization layer comprises a second metal line. The first metal via is connected with a bottom of the second metal line. The first metal via is between the first metal lines and misaligned with the first metal lines in a top view.

Abstract: A method may comprise receiving a first signal comprising first LDPC bits including systematic bits and parity bits and transmitting information indicating that the first signal was incorrectly received. A second signal comprising second LDPC bits may be received in response to the transmitting. The second signal may include LDPC bits according to a lifting size of an LDPC base graph.

Abstract: A device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ILD) layer, a reading contact, and a sensing contact. The isolation structure laterally surrounds the active region. The gate structure is across the active region. The ILD layer laterally surrounds the gate structure. The reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ILD layer. The sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ILD layer.

Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

Abstract: A semiconductor structure includes a substrate, a first nitride layer, a second nitride layer, a third nitride layer, and a polarity inversion layer. The first nitride layer is formed on the substrate, and the polarity inversion layer formed at a surface of the first nitride layer converts a non-metallic polar surface of the first nitride layer into a metallic polar surface of the polarity inversion layer. The second nitride layer is formed on the polarity inversion layer. The third nitride layer is formed on the second nitride layer.

Abstract: A device includes a detector transistor, a sensing pad, a first conductive ring, a second conductive ring, a first transistor, and a second transistor. The sensing pad is over the detector transistor. The first conductive ring is over the sending pad. The second conductive ring is over the first conductive ring. The first transistor has a source/drain region electrically coupled to the first conductive ring. The second transistor has a source/drain region electrically coupled to the second conductive ring.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A radio frequency receiving device with automatic gain control includes a filtering module, a radio frequency processing module, a controlling unit and a displaying unit. The filtering module is configured to filter a radio frequency signal to generate a filtered signal. The radio frequency processing module includes an amplifier, a detecting circuit and an automatic gain control circuit. The amplifier amplifies the filtered signal to generate a radio frequency output signal. The detecting circuit detects the filter signal to generate a detected signal. The controlling unit generates at least one intensity signal according to the detected signal, and judges the detected signal to generate an automatic gain control signal. The automatic gain control circuit controls the radio frequency output signal according to the automatic gain control signal. The displaying unit turns on or off a plurality of light emitters according to the at least one intensity signal.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.

Abstract: A three-dimensional resistive random access memory structure includes a base layer, a first layer, a second layer, a third layer and a fourth layer. The first layer includes two first conductive layers and a first via. One of the two first conductive layers is electrically connected between the base layer and the first via. The second layer includes three second conductive layers and two second vias. Two first resistive elements are formed between one of the two second vias and two of the three second conductive layers. The third layer includes three third conductive layers and two third vias. Two second resistive elements are formed between one of the two third vias and two of the three third conductive layers. The fourth layer includes a fourth conductive layer. The fourth conductive layer is electrically connected to the two third vias.

Abstract: The present application discloses an anti-electromagnetic interference wafer structure in the wafer processing stage; the anti-electromagnetic interference wafer structure comprises a digital processing unit area with a digital processing unit, an insulating layer, a conducting layer and a plurality of information connectivity points wherein the digital processing unit has a top surface on which the insulating layer and the information connectivity points are designed, the insulating layer has a top surface on which the conducting layer is coated, and the conducting layer is capable of absorbing electromagnetic interferences passed on to the conducting layer.

Abstract: A device includes a detector, a sensing pad, a ring structure, a control circuit, a first transistor, and a second transistor. The sensing pad is electrically connected to the detector. The ring structure is over the sensing pad and includes an upper conductive ring and a lower conductive ring between the upper conductive ring and the sensing pad. The first transistor interconnects the upper conductive ring and the control circuit. The second transistor interconnects the lower conductive ring and the control circuit.

Abstract: An ultraviolet light array module has a substrate, multiple ultraviolet light chips, and an amorphous silicon concentrator. The substrate has a concave. The ultraviolet light chips are arranged in an array in the concave of the substrate. The amorphous silicon concentrator covers on the concave and includes a light-transmitting base and multiple continuous light-concentrating protrusions. The optical axis of each light-concentrating protrusion aligns with the light-emitting axis of the corresponding ultraviolet light chip to generate ultraviolet light with a specific light-emitting angle. Since the light-concentrating protrusions are integrally formed on the light-transmitting base, the optical axes of the light-concentrating protrusions are close to each other and align with the light-emitting axes of the ultraviolet light chips underneath.

Abstract: Methods, systems, and devices for addressing collisions of possible random access channel (RACH) occasions. A wireless transmit receive unit (WTRU) may receive an indication of semi-static UL/DL information including configuration of RACH occasions in a remaining minimum system information (RMSI) and an indication of one or more actually transmitted synchronization signal (SS) blocks. The WTRU may then assess whether there are RACH occasions based on the configuration information and determine whether any of the RACH occasions are valid, wherein the RACH occasion may be valid based on Based on the RACH occasion is after all actually transmitted SS blocks indicated and/or whether an SS block override is disabled or enabled. The WTRU may transmit a RACH in one or more of the RACH occasions that have been determined to be valid.

Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.

Abstract: A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.