Patents by Inventor Jung Lin

Jung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12192008
    Abstract: Methods and apparatuses are described herein for Multicast/Broadcast Services (MBS). The embodiments described herein are directed to procedures for managing multiplexed MBS traffic, for prioritization between MBS related UL traffic, unicast UL traffic, and SL traffic, for handling HARQ retransmissions over C-RNTI, to support PDCP Status Reporting for MBS services, and for a wireless transmit/receive unit (WTRU) joining already started/activated Multicast Sessions. In one example, a WTRU may receive multiplexed MBS services via one or more MBS radio bearers (MRB) and/or one or more unicast data radio bearers (DRBs). The WTRU may be configured with a single Service Data Adaptation Protocol (SDAP) entity for the MBS services, and demultiplexing of traffic may be performed at the SDAP layer. The WTRU may be configured to demultiplex multiple logical channels across different MBS services, where the logical channels are received over the same transport block.
    Type: Grant
    Filed: June 28, 2024
    Date of Patent: January 7, 2025
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Rocco Di Girolamo, Pascal Adjakple, Yifan Li, Kyle Jung-Lin Pan
  • Publication number: 20240421137
    Abstract: A chip package unit, a chip package stack module, and a method of manufacturing the chip package stack module are provided. The chip package stack module includes upper and lower chip package units stacked vertically. The chip package unit includes a plurality of conductive pillars each of which has an upper pad and a lower pad respectively on upper and lower ends of the conductive pillar. The upper and lower chip package units are stacked by the lower pads of the upper chip package unit and the upper pads of the lower chip package unit electrically connected with each other. The conductive pillars of the upper chip package unit are electrically connected with the conductive pillars of the lower chip package unit correspondingly so that a memory chip of the upper chip package unit and a memory chip of the lower chip package unit are electrically connected.
    Type: Application
    Filed: April 25, 2024
    Publication date: December 19, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Patent number: 12168096
    Abstract: A ventilator-weaning timing prediction system, a program product therefor, and methods for building and using the same are disclosed to help a physician to determine a timing for a ventilator-using patient to try to weaning or completely wean from mechanical ventilation using AI-based prediction.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: December 17, 2024
    Assignee: ChiMei Medical Center
    Inventors: Jhi-Joung Wang, Hung-Jung Lin, Kuo-Chen Cheng, Shian-Chin Ko, Chin-Ming Chen, Shu-Chen Hsing, Mei-Yi Sung, Chung-Feng Liu, Chia-Jung Chen
  • Publication number: 20240410182
    Abstract: A flooring panel is provided with a quick-release adhesive sheet such that the flooring panel can be quickly attached to a support surface and removed therefrom. More particularly, the flooring panel includes a top floor layer attached or laminated to the adhesive sheet, which underlies the floor layer. The top flooring layer can be any type of flooring material, such as vinyl flooring, real or engineered wood flooring, etc.
    Type: Application
    Filed: August 16, 2024
    Publication date: December 12, 2024
    Applicants: EcoInteriors Corp., OneFlor USA, LLC
    Inventors: David J. Kim, Chi-Jung Lin
  • Publication number: 20240413020
    Abstract: A method includes forming a contact spacer on a sidewall of an inter-layer dielectric, wherein the contact spacer encircles a contact opening, forming a silicide region in the opening and on a source/drain region, depositing an adhesion layer extending into the contact opening, and performing a treatment process, so that the contact spacer is treated. The treatment process is selected from the group consisting of an oxidation process, a carbonation process, and combinations thereof. The method further includes depositing a metal barrier over the adhesion layer, depositing a metallic material to fill the contact opening, and performing a planarization process to remove excess portions of the metallic material over the inter-layer dielectric.
    Type: Application
    Filed: October 17, 2023
    Publication date: December 12, 2024
    Inventors: Min-Hsiu Hung, Chun-I Tsai, Chih-Wei Chang, Ming-Hsing Tsai, Syun-Ming Jang, Wei-Jen Lo, Wei-Jung Lin, Yu-Ting Wen, Kai-Chieh Yang
  • Patent number: 12167405
    Abstract: Methods and systems for transmitting uplink control information and feedback are disclosed for carrier aggregation systems. A user equipment device may be configured to transmit uplink control information and other feedback for several downlink component carriers using one or more uplink component carriers. The user equipment device may be configured to transmit such data using a physical uplink control channel rather than a physical uplink shared channel. The user equipment device may be configured to determine the uplink control information and feedback data that is to be transmitted, the physical uplink control channel resources to be used to transmit the uplink control information and feedback data, and how the uplink control information and feedback data may be transmitted over the physical uplink control channel.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: December 10, 2024
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Shahrokh Nayeb Nazar, Kyle Jung-Lin Pan, Robert L. Olesen, Ghyslain Pelletier, Marian Rudolf, Paul Marinier, Charles A. Dennean, Stephen G. Dick, Allan Y. Tsai, Christopher R. Cave, Chang-Soo Koo
  • Publication number: 20240405087
    Abstract: A semiconductor device includes a sensing element including a sensing electrode and a filter covering the sensing electrode. The filter includes a first work function layer and a second work function layer. The first work function layer is over the sensing electrode. The second work function layer is over the first work function layer. A work function value of the second work function layer is greater than a work function value of the first work function layer, and an atomic percentage of metal in the second work function layer is greater than an atomic percentage of metal in the first work function layer.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Ya-Chin KING, Chrong Jung LIN, Burn Jeng LIN, Yao-Hung HUANG, Wei CHANG
  • Publication number: 20240404611
    Abstract: A The memory device includes a memory array comprising a plurality of one-time-programmable (OTP) memory cells. Each of the plurality of OTP memory cells comprises: a select transistor; a diode; and a conductor fuse. The diode and the conductor fuse are coupled in series, with the select transistor coupled to a common node between the diode and the conductor fuse.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Chrong Jung Lin, Ya-Chin King, Li-Yu Wang
  • Publication number: 20240395641
    Abstract: A device in a chamber is provided. The device comprises at least one die. The at least one die comprise a first voltage generator, a dielectric layer and a first voltage regulator circuit. The first voltage generator is charged to have a first induced voltage by induced charges generated in response to a first voltage of a first electrode of a chuck in the chamber. The dielectric layer surrounds the first voltage generator to isolate the first voltage generator from the first electrode. The first voltage regulator circuit is coupled to the first voltage generator to receive the first induced voltage and generates a first power supply voltage according to the first induced voltage for a first circuit in the device.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 28, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Ya-Chin King, Chrong Jung LIN, Burn Jeng LIN, Wei CHANG
  • Publication number: 20240395874
    Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 28, 2024
    Inventors: Chun-Hsien Huang, Chang-Ting Chung, Wei-Cheng Lin, Wei-Jung Lin, Chih-Wei Chang
  • Publication number: 20240395600
    Abstract: A method for making a semiconductor device includes forming a first fin structure, a second fin structure, and a third fin structure over a substrate. The first through third fin structures all extend along a first lateral direction, and the second fin structure is disposed between the first and third fin structures. The method includes forming a mold by filling up trenches between neighboring ones of the first through third fin structures with a first dielectric material. The method includes cutting the second fin structure by removing an upper portion of the second fin structure. The method includes replacing the upper portion of the second fin structure with a second dielectric material to form a dielectric cut structure. The method includes recessing the mold to expose upper portions of the first fin structure and the third fin structure, respectively.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Cheng-Tien Chu, Chi-Wei Yang, Hsiao Wen Lee, Chih-Han Lin, Jr-Jung Lin
  • Patent number: 12155477
    Abstract: Systems, methods, and instrumentalities are disclosed for priority-based channel coding for control information. A wireless transmit/receive unit (WTRU) may sort control information associated with a first control information type into a first control information group and the control information associated with a second control information type into a second control information group, for example, based on respective priorities associated with the first and second control information types. The WTRU may group one or more bits of the first control information group into a first bit level control information group and a second bit level control information group based on priority. The WTRU may selectively apply a cyclic redundancy check (CRC) to the first control information group, the second control information group, the first bit level control information group, and/or the second bit level control information group.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: November 26, 2024
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Kyle Jung-Lin Pan, Fengjun Xi, Chunxuan Ye
  • Patent number: 12155450
    Abstract: A WTRU may include a memory and a processor. The processor may be configured to receive beam grouping information from a gNB or transmission and reception point (TRP). The beam grouping information may indicate a group of beams that the WTRU may report using group-based reporting. The group-based reporting may be a reduced level of reporting compared to a beam-based reporting. The group-based report may include measurement information for a representative beam. The representative beam may be one of the beams in the group or represents an average of the beams in the group. Alternatively, the representative beam may be a beam that has a maximum measurement value compared to other beams in the group. The group-based report may include a reference signal received power (RSRP) for the representative beam and a differential RSRP for each additional beamin the beam group.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: November 26, 2024
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Kyle Jung-Lin Pan, Fengjun Xi, Afshin Haghighat, Oghenekome Oteri, Chunxuan Ye, Frank La Sita, Robert Olesen, Moon-il Lee
  • Patent number: 12153631
    Abstract: An insight comprising a fact about a portion of data in a dataset is detected in the dataset. A context is determined by analyzing a natural language input, the context identifying an intent and an entity referenced by the natural language input. A relevance score is computed for the insight, the relevance score comprising a measure of similarity between a vector representation of the insight and a vector representation of the context, the vector representation of the insight comprising an encoding of the insight in multidimensional numerical form, the vector representation of the context comprising an encoding of the context in multidimensional numerical form. A selected insight is presented, the selected insight selected from a set of insights including the insight, the selected insight selected based on the relevance score.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 26, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abdul Quamar, Fatma Ozcan, Eser Kandogan, Jung-Lin Lee
  • Publication number: 20240387265
    Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Pin-Wen Chen, Chang-Ting Chung, Yi-Hsiang Chao, Yu-Ting Wen, Kai-Chieh Yang, Yu-Chen Ko, Peng-Hao Hsu, Ya-Yi Cheng, Min-Hsiu Hung, Chun-Hsien Huang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 12148659
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
  • Publication number: 20240380420
    Abstract: An apparatus and method are described. The apparatus includes a transceiver and processor, which attach transport block (TB) level CRC bits to a TB, select an LDPC base graph (BG) based on a code rate (CR) and TB size of the TB including TB level CRC bits, determine a number of code blocks (CBs) to use for segmenting the TB including TB level CRC bits depending on the selected LDPC BG, determine a single CB size for each of the CBs based on the number of CBs, segment the TB including TB level CRC bits into the CBs based on the number of CBs and CB size, pad zeros to a last CB of the CBs in the segmented TB, attach CB level CRC bits to each CB in the segmented TB, encode each CB in the segmented TB using the selected LDPC base graph, and transmit the encoded CBs.
    Type: Application
    Filed: July 3, 2024
    Publication date: November 14, 2024
    Applicant: INTERDIGITAL PATENT HOLDINGS, INC.
    Inventors: Chunxuan Ye, Hanqing Lou, Fengjun Xi, Kyle Jung-Lin Pan
  • Publication number: 20240379433
    Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu-Shih Wang, Ya-Yi Cheng, I-Li Chen
  • Patent number: 12142609
    Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Yao Lin, Yun-Ting Chou, Chih-Han Lin, Jr-Jung Lin
  • Patent number: D1052883
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: December 3, 2024
    Inventor: Chung-Jung Lin