Patents by Inventor Jung Lin

Jung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12142565
    Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
  • Patent number: 12142537
    Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an energy sensing film. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The energy sensing film is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the energy sensing film is contacted with an external energy source, and the induced charge is stored in the floating gate.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: November 12, 2024
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Burn-Jeng Lin, Chrong-Jung Lin, Ya-Chin King, Yi-Pei Tsai
  • Publication number: 20240370461
    Abstract: Systems and methods for providing access to information in a relational database via API-operations for dataframes, are disclosed. Exemplary implementations may: store information that represents an input dataframe; generate a first relation that represents the input dataframe, the first relation having a first schema; obtain a dataframe query to be performed on the input dataframe; translate the dataframe query into a sequence of relational database operations; perform the sequence of relational database operations on the first relation to generate a second relation; and present at least a portion of the second relation to a user, and/or perform other steps.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Balachander Atur, Hazem Elmeleegy, Jung Lin Lee, Aditya G. Parameswaran, Devin Petersohn, Mahesh Shankar Vashishtha
  • Publication number: 20240371935
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed in a recess between two adjacent channel regions, wherein the S/D feature comprises an epitaxial layer conformally deposited on an exposed surface of the recess. The structure also includes a silicide layer conformally disposed on the S/D feature, and a S/D contact disposed on the silicide layer, wherein the S/D contact has a first portion extending into the recess, and the first portion has at least three surfaces being surrounded by the silicide layer and the S/D feature.
    Type: Application
    Filed: August 25, 2023
    Publication date: November 7, 2024
    Inventors: Han-Yu Tang, Chih-Chiang Chang, Ming-Hua Yu, Chii-Horng Li, Wei-Jung Lin
  • Publication number: 20240371979
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Inventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
  • Patent number: 12136995
    Abstract: Systems, procedures, and instrumentalities are disclosed for synchronizing a signal burst, signal design, and/or system frame acquisition. A synchronization signal (SS) block or burst may be received. The SS block or burst may include a primary synchronization signal (PSS), a secondary synchronization signal (SSS), and/or a Physical Broadcast Channel (PBCH). A first cell ID may be determined and/or a plurality of SSS sequences may be generated. An m0 value (e.g., a first cyclic shift) may be determined from a set of m0 values, for example, based on the generated plurality of SSS sequences. An n1 value (e.g., a second cyclic shift) may be determined from a set of n1 values. A second cell ID may be determined, for example, based on the m0 value and the n1 value. A third cell ID may be determined, for example, based on the second cell ID and the first cell ID.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: November 5, 2024
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Kyle Jung-Lin Pan, Fengjun Xi, Robert L. Olesen, Nirav B. Shah
  • Patent number: 12137404
    Abstract: A method and apparatus for use in a base station for transmitting information blocks is disclosed. A base station transmits a plurality of beams to a wireless transmit receive unit (WTRU). Further, the base station transmits broadcast information, using a beam of the plurality of beams, the transmitted broadcast information including a first information block and a second information block. Responsive to information in the transmitted second information block, the base station may receive a random access preamble. After the reception of the random access preamble, the base station may transmit a random access response. Responsive to information in the transmitted random access response, the base station may receive a message including control information indicating additional information blocks that the WTRU is requesting to receive. After reception of the received message, the base station may transmit the additional information blocks.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: November 5, 2024
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Kyle Jung-Lin Pan, Fengjun Xi, Chunxuan Ye, Moon-Il Lee
  • Publication number: 20240363353
    Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source/drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source/drain region around the gate structure; forming an opening in the ILD layer to expose the source/drain region; forming a silicide region and a barrier layer successively in the openings over the source/drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.
    Type: Application
    Filed: August 14, 2023
    Publication date: October 31, 2024
    Inventors: Pin-Wen Chen, Yu-Chen Ko, Chi-Yuan Chen, Ya-Yi Cheng, Chun-I Tsai, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai, Syun-Ming Jang, Wei-Jen Lo
  • Publication number: 20240362110
    Abstract: A device capable of operating in a wireless communication environment. The device may be configured to determine a plurality of control signaling bits. The device may determine a plurality of cyclic redundancy check (CRC) bits based on the plurality of control signaling bits. The device may apply a channel coding scheme to the plurality of control signaling bits and the plurality of CRC bits. The plurality of CRC bits may be distributed among the plurality of control signaling bits prior to applying the channel coding scheme. The device may transmit the channel coded plurality of control signaling bits and CRC bits.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Applicant: InterDigital Technology Corporation
    Inventor: Kyle Jung-Lin Pan
  • Publication number: 20240355388
    Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, Maybe Chen, Ya-Chin King, Wen Zhang Lin, Chrong Jung Lin, Hsin-Yuan Yu
  • Publication number: 20240356680
    Abstract: Methods and apparatuses are described herein for Multicast/Broadcast Services (MBS). The embodiments described herein are directed to procedures for managing multiplexed MBS traffic, for prioritization between MBS related UL traffic, unicast UL traffic, and SL traffic, for handling HARQ retransmissions over C-RNTI, to support PDCP Status Reporting for MBS services, and for a wireless transmit/receive unit (WTRU) joining already started/activated Multicast Sessions. In one example, a WTRU may receive multiplexed MBS services via one or more MBS radio bearers (MRB) and/or one or more unicast data radio bearers (DRBs). The WTRU may be configured with a single Service Data Adaptation Protocol (SDAP) entity for the MBS services, and demultiplexing of traffic may be performed at the SDAP layer. The WTRU may be configured to demultiplex multiple logical channels across different MBS services, where the logical channels are received over the same transport block.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: InterDigital Patent Holdings, Inc.
    Inventors: Rocco Di Girolamo, Pascal Adjakple, Yifan Li, Kyle Jung-Lin Pan
  • Publication number: 20240355740
    Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 24, 2024
    Inventors: Feng-Yu Chang, Sheng-Hsuan Lin, Shu-Lan Chang, Kai-Yi Chu, Meng-Hsien Lin, Pei-Hsuan Lee, Pei Shan Chang, Chih-Chien Chi, Chun-I Tsai, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai, Syun-Ming Jang, Wei-Jen Lo
  • Patent number: 12125751
    Abstract: A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Jr-Jung Lin
  • Publication number: 20240345998
    Abstract: Systems and methods for converting dataframes to relational databases and/or vice versa, are disclosed. Exemplary implementations may: store information that represents a first dataframe; generate a first relation that represents the first dataframe, the first relation having a first schema; add a first ordering attribute to the set of attributes of the first relation; populate the first ordering attribute with numbers in accordance with a row numbering of the first dataframe; perform a relational database operation on the first relation that modifies the first relation into a second relation; create a second dataframe based on the second relation such that the row labels and the order of the rows are preserved for the (remaining) records and attributes of the second relation; and/or perform other steps.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Balachander Atur, Hazem Elmeleegy, Jung Lin Lee, Aditya G. Parameswaran, Devin Petersohn, Mahesh Shankar Vashishtha
  • Patent number: 12113122
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
  • Publication number: 20240334504
    Abstract: Method and apparatus are for coordinating data flows from multiple user apparatuses, WTRUs, in a coordinated communication group. A method comprising receiving, by a non-access stratum, NAS, layer of a wireless transmit/receive unit, WTRU, and from an application server, a coordination identifier; sending, by the WTRU and to a core network entity, a request to establish a protocol data unit, PDU, session, wherein the request comprises the coordination identifier; receiving, by the WTRU, configuration information associated with the coordination identifier and the PDU session, wherein the configuration information comprises one or more rules associated with the PDU session that are to be coordinated with one or more rules associated with other PDU sessions; and receiving, by the WTRU, from the core network entity, a message indicating establishment of the PDU session.
    Type: Application
    Filed: October 11, 2022
    Publication date: October 3, 2024
    Applicant: InterDigital Patent Holdings, Inc.
    Inventors: Catalina Mladin, Michael Starsinic, Quang Ly, Jiwan Ninglekhu, Pascal Adjakple, Kyle Jung-Lin Pan
  • Patent number: 12108448
    Abstract: Methods, systems, and apparatuses for use in wireless communication are disclosed. A method of communication on an unlicensed band may include detecting a Synchronization Signal/Physical Broadcast Channel (SS/PBCH) block comprising a demodulation references signal (DMRS), a synchronization signal (SS), and a PBCH payload. A SS/PBCH block index may be obtained from one of the DMRS and the PBCH payload. A cyclic rotation indicator may be obtained from the SS/PBCH block (e.g., from the DMRS, the SS, and/or the PBCH payload). A determination may be made that the cyclic rotation indicator indicates an on state and a time gap may be obtained from one of the DMRS and the PBCH payload, based on the determination. Frame timing may be determined based on the cyclic rotation indicator, the SS/PBCH block index, and the time gap.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: October 1, 2024
    Assignee: INTERDIGITAL PATENT HOLDINGS, INC.
    Inventors: Kyle Jung-Lin Pan, Nirav B. Shah, Fengjun Xi, Chunxuan Ye
  • Publication number: 20240323874
    Abstract: An apparatus and method for synchronization between a WTRU and a gNB are disclosed. The WTRU may receive a multiple beam synchronization signal from the gNB during synchronization. For each beam received by the WTRU, of the multiple beam synchronization signal, the WTRU may compare a received energy of the beam against a first threshold. A multiple beam synchronization signal may include a first and second synchronization signal (SS). If one or more beams of the multiple beam synchronization signal meets or exceeds the first threshold, the WTRU may report an indication of pre-synchronization to the gNB. This pre-synchronization may indicate to the gNB that a WTRU exists in an area of a particular beam of the WTRU. In this way, a gNB may target the WTRU using transmissions directed towards the WTRU.
    Type: Application
    Filed: June 3, 2024
    Publication date: September 26, 2024
    Applicant: INTERDIGITAL PATENT HOLDINGS, INC.
    Inventors: Kyle Jung-Lin Pan, Chunxuan Ye, Robert L. Olesen, Fengjun Xi
  • Publication number: 20240321653
    Abstract: A wafer package for protection of an aluminum die pad of a die from damages during probe testing process is provided. Before performing the probe testing process on a plurality of dies of the wafer package, at least one bump is disposed on a surface of the aluminum die pad of the die of the wafer package by electroless plating. The bump is a metal stack structure having a certain thickness and composed of a nickel layer and a gold layer stacked over the aluminum die pad in turn, or a nickel layer, a palladium layer, and a gold layer stacked over the aluminum die pad in turn. Thus structural strength of the aluminum die pad of the die is increased to prevent damages during the probe testing process. Therefore, quality and reliability of the dies in following operations such as wire bonding are increased.
    Type: Application
    Filed: March 22, 2024
    Publication date: September 26, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20240324474
    Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der CHIH, Wen-Zhang LIN, Yun-Sheng CHEN, Jonathan Tsung-Yung CHANG, Chrong-Jung LIN, Ya-Chin KING, Cheng-Jun LIN, Wang-Yi LEE