Patents by Inventor Jung-Sheng Hoei
Jung-Sheng Hoei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126448Abstract: Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Inventors: Animesh R. Chowdhury, Kishore K. Muchherla, Nicola Ciocchini, Akira Goda, Jung Sheng Hoei, Niccolo' Righetti, Jonathan S. Parry
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Patent number: 11922029Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.Type: GrantFiled: July 12, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Jonathan S. Parry, Nicola Ciocchini, Animesh Roy Chowdhury, Akira Goda, Jung Sheng Hoei, Niccolo' Righetti, Ugo Russo
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Publication number: 20240071522Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Nicola Ciocchini, Animesh R. Chowdhury, Kishore Kumar Muchherla, Akira Goda, Jung Sheng Hoei, Niccolo' Righetti, Jonathan S. Parry
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Patent number: 11915785Abstract: A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.Type: GrantFiled: January 26, 2021Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Jiangang Wu, Lei Zhou, Jung Sheng Hoei, Kishore Kumar Muchherla, Qisong Lin
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Publication number: 20240038311Abstract: A method includes designating a first subset of non-volatile memory with a first reliability designation, designating a second subset of non-volatile memory blocks with a second reliability designation, configuring the first subset of non-volatile memory blocks and the second subset of non-volatile memory blocks in a first verification mode, writing data to first subset of non-volatile memory blocks and the second subset of non-volatile memory blocks in the absence of write verification.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Yu-Chung Lien, Ankit V. Vashi, Zhenming Zhou, Jung Sheng Hoei
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Patent number: 11847065Abstract: A request to perform a program operation at a memory device is received. Whether a firmware block record is to be modified to correspond with a device block record is determined based on parameters associated with the program operation. The firmware block record tracks entries of the device block record. Responsive to determining that the firmware block record is to be modified, the firmware block record is modified to correspond with the device block record.Type: GrantFiled: August 24, 2021Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Mark Ish, Peng Xu
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Publication number: 20230393756Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.Type: ApplicationFiled: July 12, 2022Publication date: December 7, 2023Inventors: Kishore Kumar Muchherla, Jonathan S. Parry, Nicola Ciocchini, Animesh Roy Chowdhury, Akira Goda, Jung Sheng Hoei, Niccolo' Righetti, Ugo Russo
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Publication number: 20230386533Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.Type: ApplicationFiled: August 11, 2023Publication date: November 30, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Eric N. Lee, Kishore Kumar Muchherla, Jeffrey S. McNeil, Jung-Sheng Hoei
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Patent number: 11803321Abstract: A method can include receiving, by a first controller component of a memory sub-system, a read operation, responsive to receiving the read operation, interrupting, by the first controller component, one or more program operations being performed by the memory sub-system, receiving, by the first controller component, a control sequence from a second controller component, wherein the control sequence is based on context data associated with the interrupted one or more program operations, and performing, by the first controller component, the control sequence by copying data of the interrupted one or more program operations from a first memory location to a second memory location of a memory component associated with the memory sub-system, and performing the read operation.Type: GrantFiled: September 12, 2022Date of Patent: October 31, 2023Assignee: Micron Technology, Inc.Inventors: Horia C. Simionescu, Rohitkumar Makhija, Peng-Cheng Chen, Jung Sheng Hoei
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Patent number: 11797383Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.Type: GrantFiled: February 4, 2021Date of Patent: October 24, 2023Assignee: Micron Technology, Inc.Inventors: Jung Sheng Hoei, Sampath K. Ratnam, Renato C. Padilla, Kishore K. Muchherla, Sivagnanam Parthasarathy, Peter Feeley
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Patent number: 11776655Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: GrantFiled: October 13, 2022Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventors: Sri Rama Namala, Jung Sheng Hoei, Jianmin Huang, Ashutosh Malshe, Xiangang Luo
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Publication number: 20230297511Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.Type: ApplicationFiled: March 21, 2023Publication date: September 21, 2023Inventors: Jiangang Wu, Qisong Lin, Jung Sheng Hoei, Yunqiu Wan, Ashutosh Malshe, Peng-Cheng Chen
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Patent number: 11756594Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.Type: GrantFiled: September 1, 2021Date of Patent: September 12, 2023Assignee: Micron Technology, Inc.Inventors: Eric N. Lee, Kishore Kumar Muchherla, Jeffrey S. McNeil, Jung-Sheng Hoei
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Patent number: 11710533Abstract: A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.Type: GrantFiled: July 27, 2022Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventors: Xiaojiang Guo, Jung Sheng Hoei, Michele Piccardi, Manan Tripathi
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Publication number: 20230230624Abstract: A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.Type: ApplicationFiled: January 26, 2021Publication date: July 20, 2023Inventors: Jiangang Wu, Lei Zhou, Jung Sheng Hoei, Kishore Kumar Muchherla, Qisong Lin
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Patent number: 11698864Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.Type: GrantFiled: May 25, 2022Date of Patent: July 11, 2023Assignee: Micron Technology, Inc.Inventors: Abdelhakim Alhussien, Jiangang Wu, Karl D. Schuh, Qisong Lin, Jung Sheng Hoei
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Patent number: 11693774Abstract: A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.Type: GrantFiled: August 25, 2021Date of Patent: July 4, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Jiangang Wu, Jing Sang Liu, Jung Sheng Hoei, Kishore Kumar Muchherla, Mark Ish, Myoung Jun Go, Nolan Tran, Qisong Lin
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Patent number: 11688473Abstract: NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.Type: GrantFiled: August 6, 2020Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Scott Anthony Stoller, Jung Sheng Hoei, Ashutosh Malshe, Gianni Stephen Alsasua, Kishore Kumar Muchherla
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Patent number: 11682462Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums for compensating for charge loss effects. In some examples, a charge loss may be estimated by a charge loss monitor for a particular unit of a NAND device and may be utilized to select a charge loss compensation scheme. The charge loss may be estimated by the charge loss estimation process by determining a reference read voltage and calculating a bit count resulting from a read at that reference read voltage. The number of bits returned may be used to select the particular charge loss compensation scheme.Type: GrantFiled: July 30, 2021Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy C. Kavalipurapu, Jung Sheng Hoei
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Patent number: 11615029Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.Type: GrantFiled: December 30, 2019Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Jiangang Wu, Qisong Lin, Jung Sheng Hoei, Yunqiu Wan, Ashutosh Malshe, Peng-Cheng Chen