Patents by Inventor Jung-Sheng Hoei
Jung-Sheng Hoei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11682462Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums for compensating for charge loss effects. In some examples, a charge loss may be estimated by a charge loss monitor for a particular unit of a NAND device and may be utilized to select a charge loss compensation scheme. The charge loss may be estimated by the charge loss estimation process by determining a reference read voltage and calculating a bit count resulting from a read at that reference read voltage. The number of bits returned may be used to select the particular charge loss compensation scheme.Type: GrantFiled: July 30, 2021Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy C. Kavalipurapu, Jung Sheng Hoei
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Patent number: 11615029Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.Type: GrantFiled: December 30, 2019Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Jiangang Wu, Qisong Lin, Jung Sheng Hoei, Yunqiu Wan, Ashutosh Malshe, Peng-Cheng Chen
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Patent number: 11610632Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.Type: GrantFiled: May 26, 2021Date of Patent: March 21, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Allen Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
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Publication number: 20230065231Abstract: A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.Type: ApplicationFiled: August 25, 2021Publication date: March 2, 2023Inventors: Jiangang Wu, Jing Sang Liu, Jung Sheng Hoei, Kishore Kumar Muchherla, Mark Ish, Myoung Jun Go, Nolan Tran, Qisong Lin
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Publication number: 20230068702Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.Type: ApplicationFiled: February 2, 2022Publication date: March 2, 2023Inventors: Kishore Kumar Muchherla, Violante Moschiano, Akira Goda, Jeffrey S. McNeil, Jung Sheng Hoei, Sivagnanam Parthasarathy, James Fitzpatrick, Patrick R. Khayat
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Publication number: 20230059543Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups.Type: ApplicationFiled: August 15, 2022Publication date: February 23, 2023Inventors: Andrea Giovanni Xotta, Dheeraj Srinivasan, Ali Mohammadzadeh, Karl D. Schuh, Guido Luciano Rizzo, Jung Sheng Hoei, Michele Piccardi, Tommaso Vali, Umberto Siciliani, Rohitkumar Makhija, June Lee, Aaron S. Yip, Daniel J. Hubbard
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Publication number: 20230033870Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: ApplicationFiled: October 13, 2022Publication date: February 2, 2023Inventors: Sri Rama Namala, Jung Sheng Hoei, Jianmin Huang, Ashutosh Malshe, Xiangang Luo
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Publication number: 20230014869Abstract: A method can include receiving, by a first controller component of a memory sub-system, a read operation, responsive to receiving the read operation, interrupting, by the first controller component, one or more program operations being performed by the memory sub-system, receiving, by the first controller component, a control sequence from a second controller component, wherein the control sequence is based on context data associated with the interrupted one or more program operations, and performing, by the first controller component, the control sequence by copying data of the interrupted one or more program operations from a first memory location to a second memory location of a memory component associated with the memory sub-system, and performing the read operation.Type: ApplicationFiled: September 12, 2022Publication date: January 19, 2023Inventors: Horia C. Simionescu, Rohitkumar Makhija, Peng-Cheng Chen, Jung Sheng Hoei
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Publication number: 20230019189Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Inventors: Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Kishore Kumar Muchherla
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Patent number: 11556251Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.Type: GrantFiled: February 26, 2021Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Ali Mohammadzadeh, Jung Sheng Hoei, Dheeraj Srinivasan, Terry M. Grunzke
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Publication number: 20220367000Abstract: A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: Xiaojiang Guo, Jung Sheng Hoei, Michele Piccardi, Manan Tripathi
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Patent number: 11488670Abstract: Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.Type: GrantFiled: February 22, 2021Date of Patent: November 1, 2022Assignee: Micron Technology, Inc.Inventors: Xiangang Luo, Jianmin Huang, Jung Sheng Hoei, Harish Reddy Singidi, Ting Luo, Ankit Vinod Vashi
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Patent number: 11475974Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: GrantFiled: August 4, 2021Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventors: Sri Rama Namala, Jung Sheng Hoei, Jianmin Huang, Ashutosh Malshe, Xiangang Luo
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Patent number: 11455109Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.Type: GrantFiled: January 27, 2021Date of Patent: September 27, 2022Assignee: Micron Technology, Inc.Inventors: Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Kishore Kumar Muchherla
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Patent number: 11442656Abstract: An indication that one or more program operations have been interrupted as a result of a read operation can be received at a first controller component associated with a memory sub-system. Context data associated with interrupted program operations can be received at the first controller component. A control sequence based on the context data can be generated at the first controller component. The control sequence can indicate how a second controller component associated with the memory sub-system interacts with a memory component of the memory sub-system to perform the read operation and to resume the interrupted program operations. The control sequence can further specify one or more additional operations that are associated with copying data of the interrupted program operations between first and second memory locations of the memory component. The control sequence can be provided to the second controller component.Type: GrantFiled: February 22, 2021Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventors: Horia C. Simionescu, Rohitkumar Makhija, Peng-Cheng Chen, Jung Sheng Hoei
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Publication number: 20220283952Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.Type: ApplicationFiled: May 25, 2022Publication date: September 8, 2022Inventors: Abdelhakim Alhussien, Jiangang Wu, Karl D. Schuh, Qisong Lin, Jung Sheng Hoei
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Patent number: 11437117Abstract: A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to the program voltage target; a sensor circuit that compares a duty cycle of the control signal to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.Type: GrantFiled: May 29, 2020Date of Patent: September 6, 2022Assignee: Micron Technology, Inc.Inventors: Xiaojiang Guo, Jung Sheng Hoei, Michele Piccardi, Manan Tripathi
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Patent number: 11416154Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.Type: GrantFiled: December 16, 2020Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
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Publication number: 20220236871Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.Type: ApplicationFiled: January 27, 2021Publication date: July 28, 2022Inventors: Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Kishore Kumar Muchherla
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Publication number: 20220199189Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: ApplicationFiled: August 4, 2021Publication date: June 23, 2022Inventors: Sri Rama Namala, Jung Sheng Hoei, Jianmin Huang, Ashutosh Malshe, Xiangang Luo