Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

Abstract: A processing device in a memory system incrementally adjusts a center read voltage for a first block of a memory device by a first offset amount to generate an adjusted read voltage and causes the adjusted read voltage to be applied to the first block to determine an adjusted bit count associated with the adjusted read voltage. The processing device further determines whether a difference between the adjusted bit count and a previous bit count associated with a previous read voltage satisfies a first threshold criterion pertaining to an error threshold, and responsive to the difference between the adjusted bit count and the previous bit count not satisfying the first threshold criterion, determines a read window for the first block based on the previous read voltage.

Abstract: A request to perform a program operation at a memory device is received. Whether a firmware block record is to be modified to correspond with a device block record is determined based on parameters associated with the program operation. The firmware block record tracks entries of the device block record. Responsive to determining that the firmware block record is to be modified, the firmware block record is modified to correspond with the device block record.

Abstract: A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to the program voltage target; a sensor circuit that compares a duty cycle of the control signal to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums for compensating for charge loss effects. In some examples, a charge loss may be estimated by a charge loss monitor for a particular unit of a NAND device and may be utilized to select a charge loss compensation scheme. The charge loss may be estimated by the charge loss estimation process by determining a reference read voltage and calculating a bit count resulting from a read at that reference read voltage. The number of bits returned may be used to select the particular charge loss compensation scheme.

Abstract: The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.

Abstract: A request to perform a program operation at a memory device is received. An entry of a device block record stored at the memory device is determined to be removed based on parameters associated with the program operation and a firmware block record that corresponds to the device block record. The firmware block record tracks the entries of the device block record. The entries of the device block record are associated with blocks of the memory device and identify start voltages that are applied to wordlines of the blocks to program memory cells associated with the wordlines. A command is submitted to the memory device to remove the entry associated with a particular block from the device block record and to make a space available at the device block record for a new entry associated with a new block that is to be written in view of the program operation.

Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums for compensating for charge loss effects. In some examples, a charge loss may be estimated by a charge loss monitor for a particular unit of a NAND device and may be utilized to select a charge loss compensation scheme. The charge loss may be estimated by the charge loss estimation process by determining a reference read voltage and calculating a bit count resulting from a read at that reference read voltage. The number of bits returned may be used to select the particular charge loss compensation scheme.

Abstract: A request to perform a program operation at a memory device is received. An entry of a device block record stored at the memory device is determined to be removed based on parameters associated with the program operation and a firmware block record that corresponds to the device block record. The firmware block record tracks the entries of the device block record. The entries of the device block record are associated with blocks of the memory device and identify start voltages that are applied to wordlines of the blocks to program memory cells associated with the wordlines. A command is submitted to the memory device to remove the entry associated with a particular block from the device block record and to make a space available at the device block record for a new entry associated with a new block that is to be written in view of the program operation.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums for compensating for charge loss effects. In some examples, a charge loss may be estimated by a charge loss monitor for a particular unit of a NAND device and may be utilized to select a charge loss compensation scheme. The charge loss may be estimated by the charge loss estimation process by determining a reference read voltage and calculating a bit count resulting from a read at that reference read voltage. The number of bits returned may be used to select the particular charge loss compensation scheme.

Abstract: An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.

Abstract: The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.