Patents by Inventor Jung Wang

Jung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200136026
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Application
    Filed: October 25, 2018
    Publication date: April 30, 2020
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: 10636864
    Abstract: A display is provided. The display device includes a display area and a non-display area located around the display area; a base layer; an organic light-emitting diode (OLED) that is located on the base layer in the display area; and a first crack detection line that is located on the base layer in the non-display area; wherein the first crack detection line comprises a first line that extends substantially in a first direction along a first edge of the display area, a second line that is separated from the first line and extends substantially in the first direction, and a third line that is connected to an end of the first line and an end of the second line, wherein a cross-sectional shape of the first line in a second direction crossing the first direction is inversely tapered.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: April 28, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hun Kim, Yong Jin Kim, Soon Jung Wang, Keun Soo Lee, Jae Ho Lee, Kyung Chan Chae
  • Publication number: 20200117257
    Abstract: A power control device including a main battery, an auxiliary battery, a charging circuit, and a control circuit, for supplying power to a load is proposed. The main battery supplies power to the load. A volume, a capacity, and an output voltage of the auxiliary battery are all less than those of the main battery. The charging circuit receives a power input signal from a power supply network via a power adapter. The charging circuit generates a protection signal when changing from a first state that receives the power input signal to a second state that does not receive the power input signal. The control circuit controls the auxiliary battery to supply power to the load via a boosting circuit when receiving the protection signal, where a second output voltage outputted by the auxiliary battery is greater than or equal to a first output voltage outputted by the main battery.
    Type: Application
    Filed: July 1, 2019
    Publication date: April 16, 2020
    Applicant: Acer Incorporated
    Inventors: Shuo-Jung Chou, Chuan-Jung Wang, Chih-Chiang Chen
  • Patent number: 10614209
    Abstract: A software risk evaluation system and method thereof are provided. The software risk evaluation system includes a computer system and a server. The computer system executes a software risk evaluation program to perform the steps of: scanning the computer system to obtain a software installation list of software installed on the computer system; obtaining a software risk management file from the server; setting a risk level for each software on the software installation list according to the software risk management file; adjusting the risk level of each software on the software installation list according to software asset management data and the software risk management file; and generating a software risk evaluation report according to the adjusted risk level of each software on the software installation list.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: April 7, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Tu-Jung Li, Chen-Chung Lee, Mei-Jung Wang, Hung-Yu Yang, Ming-Jen Chen, Chia-Hung Lin
  • Publication number: 20200106007
    Abstract: A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.
    Type: Application
    Filed: November 16, 2018
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
  • Publication number: 20200106008
    Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
    Type: Application
    Filed: April 1, 2019
    Publication date: April 2, 2020
    Inventors: Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Chih-Yuan Ting
  • Patent number: 10601176
    Abstract: A connecting device includes a base, a locking member, linkage, and a detector. The locking member is rotatably disposed on the base and configured to rotate about an axis to a locked position along a first rotational direction and to an unlocked position along a second rotational direction opposite to the first rotational direction. The locking member has an engaging portion at a peripheral edge thereof. The linkage is rotatably disposed on the base and includes an abutting portion configured to abut against the peripheral edge. When the locking member is rotated to the locked position, the abutting portion is moved to and is engaged with the engaging portion accompanied with a rotation of the linkage. The detector is disposed on the base and configured to detect the rotation of the linkage.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: March 24, 2020
    Assignee: Gogoro Inc.
    Inventors: Zih-Wei Chen, Yu-Jung Wang, Chen-Hsin Hsu
  • Patent number: 10589905
    Abstract: An airtight container has a lid which is easily opened by the principle of the lever thus preventing broth from splashing out when the lid is opened. The airtight container includes a container body having a latching bump and a bent flange, a rotating knob connected to the flange and having an opening-closing plate and a step portion, and a lid having a latching protrusion, a downwardly bent flange and a lid extension portion, wherein, when the rotating knob is just rotated upward in a state where the lid is coupled to the container body, the opening-closing plate lifts the lid extension portion by “the principle of the lever” while the step portion prevents the lid extension portion from spreading outwards, thereby allowing the latching protrusion to be released from the latching bump and the lid to be opened from the container body.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: March 17, 2020
    Inventors: Soo Jung Wang, Young Bin Wang, Bang Hyang Song
  • Publication number: 20200075449
    Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: PEI-HAW TSAO, CHIEN-JUNG WANG
  • Publication number: 20200066580
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 27, 2020
    Inventors: Tai-Yen PENG, Chang-Sheng LIN, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH
  • Publication number: 20200058847
    Abstract: A perpendicularly magnetized spin-orbit magnetic device including a heavy metal layer, a magnetic tunnel junction, a first antiferromagnetic layer, a first block layer and a first stray field applying layer is provided. The magnetic tunnel junction is disposed on the heavy metal layer. The first block layer is disposed between the magnetic tunnel junction and the first antiferromagnetic layer. The first stray field applying layer is disposed between the first antiferromagnetic layer and the first block layer. The magnetic tunnel junction comprises a free layer, a tunneling barrier layer, and pinned layer. The tunneling barrier layer is disposed on the free layer. The pinned layer is disposed on the tunneling barrier layer. A film plane area of the free layer is greater than a film plane area of the tunneling barrier layer and a film plane area of the pinned layer.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 20, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Han Lee, Shan-Yi Yang, Yao-Jen Chang, I-Jung Wang, Jeng-Hua Wei
  • Publication number: 20200057361
    Abstract: A light source module of a photo printer includes a first micro light source, a second micro light source, a rod lens array and a microlens. The first micro light source emits a first light beam. The second micro light source emits a second light beam. The rod lens array is arranged between the first micro light source, the second micro light source and a film paper. The microlens is arranged between the first micro light source, the second micro light source and the rod lens array. The microlens is used for converging the projection angles of the first light beams and the second light beam. The microlens has an optical axis. The second micro light source is arranged along the optical axis. The first micro light source is arranged beside a first side of the optical axis.
    Type: Application
    Filed: May 28, 2019
    Publication date: February 20, 2020
    Inventors: Yun-Yi Lin, Mu-Jung Wang
  • Patent number: 10553150
    Abstract: A display device is provided and includes: a display panel; and a circuit board electrically connected to the display panel and including: a substrate; a first conductive layer disposed on the substrate and including a first connecting pad and a second connecting pad; a second conductive layer disposed on and electrically connected to the second connecting pad; a first electronic component disposed on and electrically connected to the first connecting pad; and a second electronic component disposed on the second conductive layer and electrically connected to the second connecting pad through the second conductive layer. The first connecting pad has a first thickness. A total thickness of the second connecting pad and the second conductive layer is a second thickness. The second thickness is greater than the first thickness. A ratio of the second thickness to the first thickness ranges from 1.2 to 5000.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: February 4, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Chieh Fan, Wen-Chieh Lin, Tong-Jung Wang
  • Publication number: 20200035907
    Abstract: The present disclosure provides a semiconductor structure, including a bottom electrode via, a top surface of the bottom electrode via having a first width, a barrier layer surrounding the bottom electrode via, and a magnetic tunneling junction (MTJ) over the bottom electrode via, a bottom of the MTJ having a second width, the first width being narrower than the second width.
    Type: Application
    Filed: January 8, 2019
    Publication date: January 30, 2020
    Inventors: TAI-YEN PENG, YU-SHU CHEN, CHIEN CHUNG HUANG, SIN-YI YANG, CHEN-JUNG WANG, HAN-TING LIN, JYU-HORNG SHIEH, QIANG FU
  • Patent number: 10546622
    Abstract: A spin-orbit torque MRAM is provided. The spin-orbit torque MRAM includes a spin Hall metal layer, a free magnetic layer disposed on the spin Hall metal layer, a barrier layer, and a pinned layer. The free magnetic layer includes a first area and a second area located on both sides thereof. The barrier layer includes a first area and a second area located on both sides thereof. The first area of the barrier layer is disposed on that of the free magnetic layer, and the second area of the barrier layer is disposed on that of the free magnetic layer. The pinned layer is disposed on the first area of the barrier layer.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: January 28, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Sheng Chen, I-Jung Wang
  • Publication number: 20200027933
    Abstract: A display device includes a substrate having a display area and a non-display area located at an outer periphery of the display area; a transistor layer disposed on the substrate; a plurality of partition walls disposed on the transistor layer in the display area; a light emitting element disposed between the partition walls; and a spacer configured to be disposed in the non-display area of the substrate, wherein the spacer may include a spacer body disposed on the same layer as the partition walls and on at least a portion of the transistor layer.
    Type: Application
    Filed: March 8, 2019
    Publication date: January 23, 2020
    Inventors: Ji Hye Heo, Soon Jung Wang, Eun Ju Lee
  • Patent number: 10488690
    Abstract: A display device includes a display panel, a first frame, a second frame and an adhesive element. The first frame is disposed corresponding to the display panel and includes a bottom portion and a side wall. The bottom portion is connected to the side wall. The second frame is disposed on the first frame. The display panel is disposed on a part of the second frame. The adhesive element is disposed between the first frame and the second frame. The adhesive element contacts at least a part of the bottom portion and at least a part of the side wall. An assembling method of the display device is also provided.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: November 26, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Chih-Chiao Yang, Chia-Chun Yang, Chin-Cheng Kuo, Tong-Jung Wang
  • Patent number: 10483782
    Abstract: A battery control method and a battery control apparatus are provided. The battery control method includes the following steps. Whether a charging voltage value of a battery is greater than a voltage threshold is determined. When the charging voltage value is greater than the voltage threshold, a battery temperature of the battery is obtained. When the battery temperature is less than a first temperature, a time parameter is accumulated according to a first accumulating rate. When the time parameter reaches a time threshold, the charging voltage value of the battery is reduced.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: November 19, 2019
    Assignee: ACER INCORPORATED
    Inventors: Shuo-Jung Chou, Chuan-Jung Wang
  • Patent number: 10475719
    Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, Chien-Jung Wang
  • Publication number: 20190306990
    Abstract: A display device is provided. The display device includes a display panel, a flexible circuit board, an integrated circuit, and a conductive layer. The flexible circuit board is electrically connected with the display panel and includes a plurality of conductive wires. The integrated circuit is disposed on the flexible circuit board and has a plurality of bumps. The conductive layer is disposed between the integrated circuit and the flexible circuit board and covers a periphery of the integrated circuit. In addition, the conductive layer includes an adhesive and a plurality of conductive particles distributed in the adhesive. Moreover, the bumps are electrically connected with the conductive wires through the conductive particles.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Applicant: Innolux Corporation
    Inventors: Wei-Cheng Chu, Chia-Cheng Liu, Chih-Yuan Lee, Chin-Lung Ting, Tong-Jung Wang