Abstract: A method of forming a semiconductor device using selective epitaxial growth (SEG) is provided. This method includes forming an insulating layer pattern having a window on a semiconductor substrate. The window exposes a predetermined region of the semiconductor substrate. The substrate having the window is cleaned, thereby removing any native oxide layer on the exposed substrate. The cleaned substrate is oxidized. Accordingly, a sacrificial oxide layer is formed thereon. The sacrificial oxide layer is removed. Thus, the exposed substrate has substantially no crystalline defects. A single crystalline semiconductor layer is then grown on the exposed substrate using SEG.

Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

Abstract: A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.

Abstract: A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium single crystalline layer or a dual layer in which a silicon-germanium single crystalline layer covers a silicon single crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium single crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a single crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium single crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium single crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode.

Abstract: An internal clock generating circuit and method for generating an internal clock phase-synchronized to an input clock with minimum delay and at high speed is disclosed. An internal clock generating circuit comprises a first delay control circuit for generating a first clock having the time delay of up to T/2 (where T is a cycle of an input clock) from the input clock and for generating a first variable delay control signal; and a second delay control circuit for generating a second clock in response to the first variable delay control signal, the second clock having the time delay of greater than T/2 from the input clock at an initial state and having the time delay of about T from the input clock in a phase-locked state.

Abstract: A delay circuit having a constant period of delay time independent of changes in operations, temperature and voltage includes a current source for generating a constant current and having PMOS transistors of which gates are commonly connected, wherein the constant current is controlled by sizes of the PMOS transistors; and a unit delay circuit including a CMOS inverter having PMOS and NMOS transistors, wherein non-adjacent PMOS and NMOS transistors are controlled to charge and discharge current when a constant level of the constant current is transmitted from the current source and other adjacent PMOS and NMOS transistors are switched to connect or disconnect a current path through which the current is charged or discharged.

Abstract: The invention relates to a semiconductor memory device and a method for generating an internal clock, the circuit of the semiconductor device including: a receiver for receiving an external clock; a delay compensation circuit for receiving an output of the receiver and delaying it by as much as the compensation delay time and control delay time subtracted out of a cycle of the external clock; an external control delay part for delaying an output of the delay compensation circuit by as much as the control delay time and unit increase/decrease delay time in response to an external control code; and an internal clock driver for driving an output of the external control delay part and generating an internal clock centered to externally applied data, thereby performing an accurate timing control to an external clock without loss of performance.

Abstract: A circuit includes a clock buffer to generate an initial reference clock signal responsive to an external clock signal, a DMC to receive the initial reference clock signal, and an array of forward units to receive a signal from the DMC. The circuit also includes an array of back units that produces a back signal. The back signal is input in a clock driver to produce an internal clock signal. A delay element produces a delayed reference signal responsive to the initial reference clock signal. A plurality of MCCs receive an output of one of the forward units and the delayed reference clock signal. When one of the outputs of the forward units is synchronized with the delayed reference clock signal, one of the back units is thereby activated, which initiates generation of the back signal.

Abstract: An HF power device in an HF transistor includes a semiconductor layer as a first conductive type, a field area formed in a trench structure on one side of the semiconductor layer, gate electrode formed on a given surface of the semiconductor layer, a channel layer as a second conductive type laterally diffused from the field area to a width containing both sides of the gate electrode, and formed on the surface of the semiconductor layer, a source area as the second conductive type formed within the channel layer between one side of the gate electrode and the field area, a drain area as the second conductive type formed on the surface of the semiconductor layer with a given interval from another side of the gate electrode, a sinker as the first conductive type provided as a column shape of a trench structure for dividing into two source areas by a piercing through the source area, and connected to the semiconductor layer, an LDD area as the second conductive type formed on the surface of the semiconductor laye

Abstract: A method of forming a semiconductor device using selective epitaxial growth (SEG) is provided. This method includes forming an insulating layer pattern having a window on a semiconductor substrate. The window exposes a predetermined region of the semiconductor substrate. The substrate having the window is cleaned, thereby removing any native oxide layer on the exposed substrate. The cleaned substrate is oxidized. Accordingly, a sacrificial oxide layer is formed thereon. The sacrificial oxide layer is removed. Thus, the exposed substrate has substantially no crystalline defects. A single crystalline semiconductor layer is then grown on the exposed substrate using SEG.

Abstract: A delay circuit having a constant period of delay time independent of changes in operations, temperature and voltage includes a current source for generating a constant current and having PMOS transistors of which gates are commonly connected, wherein the constant current is controlled by sizes of the PMOS transistors; and a unit delay circuit including a CMOS inverter having PMOS and NMOS transistors, wherein non-adjacent PMOS and NMOS transistors are controlled to charge and discharge current when a constant level of the constant current is transmitted from the current source and other adjacent PMOS and NMOS transistors are switched to connect or disconnect a current path through which the current is charged or discharged.

Abstract: A method of forming polycrystalline silicon germanium gate electrode is disclosed. The method include the steps of forming gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma doping of germanium to the polycrystalline silicon layer. Generally, boron is doped to the polycrystalline silicon after the step of the plasma doping of germanium. The process of plasma doping of germanium comprises the step of forming germanium contained plasma and enhancing bias electric potential to substrate for the formulated germanium plasma to be accelerated and injected to the polycrystalline silicon layer revealed. If the present invention is applied to CMOS transistor device, doping mask for the germanium plasma doping can be used.

Abstract: A method of selective epitaxial growth performed by sequentially and repeatedly introducing a source gas, an etching gas, and a reducing gas in the reaction chamber, wherein controlled epitaxial layer doping may be obtained by introducing a dopant source gas during introducing any one of the source gas, an etching gas, and a reducing gas, and thereby producing a smooth and uniform epitaxial layer on a predetermined region of a semiconductor substrate.

Abstract: An HF power device in an HF transistor includes a semiconductor layer as a first conductive type, a field area formed in a trench structure on one side of the semiconductor layer, gate electrode formed on a given surface of the semiconductor layer, a channel layer as a second conductive type laterally diffused from the field area to a width containing both sides of the gate electrode, and formed on the surface of the semiconductor layer, a source area as the second conductive type formed within the channel layer between one side of the gate electrode and the field area, a drain area as the second conductive type formed on the surface of the semiconductor layer with a given interval from another side of the gate electrode, a sinker as the first conductive type provided as a column shape of a trench structure for dividing into two source areas by a piercing through the source area, and connected to the semiconductor layer, an LDD area as the second conductive type formed on the surface of the semiconductor laye

Abstract: A method of selective epitaxial growth performed by sequentially and repeatedly introducing a source gas, an etching gas, and a reducing gas in the reaction chamber, wherein controlled epitaxial layer doping may be obtained by introducing a dopant source gas during introducing any one of the source gas, an etching gas, and a reducing gas, and thereby producing a smooth and uniform epitaxial layer on a predetermined region of a semiconductor substrate.

Abstract: A reverse self-aligned field effect transistor and a method of fabricating the same are provided. The reverse self-aligned transistor includes a source formed on an active region of a semiconductor substrate and a drain formed on the active region of the semiconductor substrate, the drain being positioned a predetermined distance from the source. A silicide film is formed on the source and the drain. Insulative film spacers are formed on sidewalls of a trench, the trench being formed by etchin the semiconductor substrate between the source and the drain. A gate insulative film is formed on a lower portion of the trench and a metal gate is formed on the gate insulative film between the insulative film spacers. The metal gate is electrically isolated from the source and the drain by the insulative film spacers.

Abstract: An improved door lock is disclosed whereby the application of excessive force on the door handle will not cause a malfunction of the door lock and will not cause damage to the internal working features of the door lock. The door lock includes an outer rose spindle assembly, having an inner and an outer spindle, wherein the two spindle portions are releasably connected by a plurality of complementary pins and dints. Upon the application of excessive force on the door handle, the pins are released from the dints such that the force is not further transmitted to sequential features of the lock body.