Patents by Inventor Junghyun Cho

Junghyun Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11328903
    Abstract: A plasma processing system includes a radio-frequency (RF) power source unit configured to generate three RF powers; a process chamber to which a process gas supplied and to which the RF powers are applied to generate a plasma; and an impedance matcher between the RF power source unit and the process chamber, the impedance matcher configured to adjust an impedance. The RF power source unit may include a first RF power source connected to a first electrode located in a lower portion of the process chamber to apply a first RF power having a first frequency, a second RF power source connected to the first electrode and to apply a second RF power having a second frequency, and a third RF power source connected to a second electrode located in an upper portion of the process chamber and to apply a third RF power having a third frequency.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaewon Jeong, Daebeom Lee, Juho Lee, Junghyun Cho
  • Patent number: 11322579
    Abstract: A semiconductor device includes a substrate and memory cell arrays arranged on the substrate in a first direction and second direction. The first direction and second direction are parallel to a top surface of the substrate and intersect each other. The memory cell arrays include a plurality of memory cells. A cell dummy pattern on the substrate is arranged between the memory cell arrays in at least one of the first direction and second direction and extends along a side of the memory cell arrays. A cell conductive pattern is included on the substrate. A cell contact plug is configured to connect the cell dummy pattern and the cell conductive pattern. The cell contact plug is arranged between the cell dummy pattern and the cell conductive pattern in a third direction that is perpendicular to the first direction and the second direction.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Song Yi Kim, Junghyun Cho
  • Patent number: 11296148
    Abstract: A variable resistance memory device including a substrate; first and second transistors on the substrate; first conductive lines on the transistors, each of the first conductive lines extending in a first direction, and the first conductive lines being spaced apart from each other; first contact plugs directly contacting substrate-facing surfaces of the first conductive lines, the first contact plugs being electrically connected to the first transistors, respectively; second conductive lines on the first conductive lines, each of the second conductive lines extending in the second direction, and the second conductive lines being spaced apart from each other; second contact plugs directly contacting substrate-facing surfaces of the second conductive lines, the second contact plugs being electrically connected to the second transistors, respectively; and memory units between the conductive lines, wherein each of the second contact plugs does not overlap with any of the memory units in the third direction.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Junghyun Cho
  • Patent number: 11289684
    Abstract: A display device includes: a substrate; two pixel circuits on the substrate spaced apart from each other with a transmission area therebetween, each of the two pixel circuits including a transistor and a storage capacitor; two display elements respectively electrically coupled to the two pixel circuits; a bottom metal layer between the substrate and the two pixel circuits and including a through hole at the transmission area; an encapsulation member on the two display elements; and an optical functional layer on the encapsulation member, wherein the optical functional layer includes: a first layer including a first opening, second openings, and a first slope portion, the first opening at the transmission area, the second openings corresponding to each of the two display elements, and the first slope portion being around the transmission area; and a second layer on the first layer.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 29, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Junghyun Cho, Seunghoon Lee, Jinkoo Chung, Beohmrock Choi
  • Publication number: 20220036066
    Abstract: Disclosed are an X-RAY image reading support method including the steps of acquiring a target X-RAY image photographed by transmitting or reflecting X-RAY in a reading space in which an object to be read is disposed; applying the target X-RAY image to a reading model that extracts features from an input image; and identifying the object to be read as an object corresponding to a classified class when the object to be read is classified as a set class based on a first feature set extracted from the target X-RAY image, and an X-RAY image reading support system performing the method.
    Type: Application
    Filed: November 25, 2020
    Publication date: February 3, 2022
    Inventors: Junghyun CHO, Hyunwoo CHO, Haesol PARK, Ig Jae KIM
  • Patent number: 11233103
    Abstract: An organic light-emitting display apparatus includes a substrate; thin film transistors; a protective layer that includes a plurality of concave-convex units disposed in a pixel area; an organic light-emitting device disposed on the protective layer; and an encapsulation unit that covers the organic light-emitting device. Each of the concave-convex units protrudes from a surface of the protective layer. The organic light-emitting device includes a pixel electrode, an emission layer, and an opposite layer sequentially stacked on the concave-convex unit, and a distance between the pixel electrode and the opposite electrode is determined by 5%?(a/b)?18%, wherein ‘a’ is a vertical distance with respect to the surface of the protective layer between the pixel electrode and the opposite electrode and ‘b’ is a minimum distance between the pixel electrode and the opposite electrode.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kiyoung Yeon, Haeyoung Yun, Junghyun Cho, Younggil Park, Dongyoun Yoo, Wooyoung Lee, Sooim Jeong
  • Publication number: 20220013607
    Abstract: A display apparatus includes a substrate including a display area and a peripheral area outside the display area, a display element arranged on the substrate in the display area, an encapsulation layer arranged on the display element, a first insulating layer arranged on the encapsulation layer and including a first opening that corresponds to a light-emitting area of the display element, and a second insulating layer covering the first insulating layer. A second refractive index of the second insulating layer is greater than a first refractive index of the first insulating layer, and a side surface of the first insulating layer defining the first opening includes a staircase-shaped step.
    Type: Application
    Filed: December 28, 2020
    Publication date: January 13, 2022
    Inventors: Wangwoo Lee, Minwoo Woo, Gunwoo Ko, Haeyoung Yun, Hyungjoo Jeon, Junghyun Cho
  • Publication number: 20220005869
    Abstract: A semiconductor memory device is disclosed. The device may include a device isolation layer in a substrate to define first and second active portions, a first contact on the substrate, first and second memory cells spaced apart from the first contact in a first direction by first and second distances, respectively, first and second conductive lines connected to the first and second memory cells, respectively, and extending in a second direction, and first and second selection transistors respectively connected to the first and second conductive lines. A length of a bottom surface of a first gate electrode of the first selection transistor overlapping the first active portion in a third direction may be different from a length of a bottom surface of a second gate electrode of the second selection transistor overlapping the second active portion in the third direction.
    Type: Application
    Filed: April 16, 2021
    Publication date: January 6, 2022
    Inventors: SONG YI KIM, JUNGHYUN CHO
  • Publication number: 20210399262
    Abstract: Provided is a display apparatus having improved reliability by effectively controlling spreading of an organic layer. The display apparatus includes a substrate including a display area, and a peripheral area outside the display area, a display element at the display area, an input-sensing layer over the display element, and an optical functional layer on the input-sensing layer, and including a first layer, which corresponds to the display area and the peripheral area, and a second layer on the first layer, and having a greater refractive index than the first layer, wherein the first layer defines a first valley portion defining first holes that is on the peripheral area, and that surrounds the second layer.
    Type: Application
    Filed: June 2, 2021
    Publication date: December 23, 2021
    Inventors: Minwoo Woo, Gunwoo Ko, Wangwoo Lee, Junghyun Cho, Kangwook Heo
  • Publication number: 20210366743
    Abstract: A semiconductor packaging apparatus and methods of manufacturing semiconductor devices using the same. The semiconductor packaging apparatus includes a process unit, and a controller associated with the process unit. The process unit includes a bonding part that bonds a semiconductor substrate and a carrier substrate to each other to form a bonded substrate, a cooling part that cools the bonded substrate, and a detection part in the cooling part and configured to detect a defect of the bonded substrate. The controller is configured to control the process unit using data obtained from the detection part.
    Type: Application
    Filed: June 3, 2021
    Publication date: November 25, 2021
    Inventors: JUNGHYUN CHO, SANG-GEUN PARK, DONGSEOK BAEK, JAEHYUK CHOI
  • Publication number: 20210351011
    Abstract: A plasma processing system includes a radio-frequency (RF) power source unit configured to generate three RF powers; a process chamber to which a process gas supplied and to which the RF powers are applied to generate a plasma; and an impedance matcher between the RF power source unit and the process chamber, the impedance matcher configured to adjust an impedance. The RF power source unit may include a first RF power source connected to a first electrode located in a lower portion of the process chamber to apply a first RF power having a first frequency, a second RF power source connected to the first electrode and to apply a second RF power having a second frequency, and a third RF power source connected to a second electrode located in an upper portion of the process chamber and to apply a third RF power having a third frequency.
    Type: Application
    Filed: November 16, 2020
    Publication date: November 11, 2021
    Inventors: Jaewon JEONG, Daebeom LEE, Juho LEE, Junghyun CHO
  • Publication number: 20210296222
    Abstract: A method of manufacturing a semiconductor package includes preparing a core substrate having an upper surface and a lower surface, and including a cavity. A passive component is disposed in the cavity. A first insulating layer is formed on the upper surface of the core substrate and in the cavity and encapsulates the passive component. Through-vias are formed that penetrate the core substrate and the first insulating layer, and a first wiring layer is formed on the first insulating layer. The first wiring layer connects the through-vias and the passive component. A connection structure including an insulating member is formed on the first insulating layer and a redistribution layer is formed in the insulating member. The redistribution layer is connected to the first wiring layer. A semiconductor chip is disposed on an upper surface of the connection structure. The semiconductor chip has connection pads connected to the redistribution layer.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 23, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghyun CHO, Youngsik Hur, Youngkwan Lee, Jongrok Kim
  • Publication number: 20210249635
    Abstract: A display device includes: a substrate; two pixel circuits on the substrate spaced apart from each other with a transmission area therebetween, each of the two pixel circuits including a transistor and a storage capacitor; two display elements respectively electrically coupled to the two pixel circuits; a bottom metal layer between the substrate and the two pixel circuits and including a through hole at the transmission area; an encapsulation member on the two display elements; and an optical functional layer on the encapsulation member, wherein the optical functional layer includes: a first layer including a first opening, second openings, and a first slope portion, the first opening at the transmission area, the second openings corresponding to each of the two display elements, and the first slope portion being around the transmission area; and a second layer on the first layer.
    Type: Application
    Filed: September 17, 2020
    Publication date: August 12, 2021
    Inventors: Junghyun CHO, Seunghoon LEE, Jinkoo CHUNG, Beohmrock CHOI
  • Publication number: 20210241463
    Abstract: Embodiments relate to a method for supporting X-ray image reading including receiving information associated with a reading target positioned in a reading space where X-rays pass through or are reflected off, acquiring a non X-RAY image of an item object based on the information associated with the reading target, and generating a fake X-RAY image of the item object by applying the non X-RAY image of the item object to the image transform model, and a system for performing the same.
    Type: Application
    Filed: November 24, 2020
    Publication date: August 5, 2021
    Inventors: Junghyun CHO, Ig Jae KIM, Hyunwoo CHO, Haesol PARK
  • Patent number: 11075089
    Abstract: Disclosed are a method of plasma etching and a method of fabricating a semiconductor device including the same. The method of plasma etching includes loading a substrate including an etch target onto a first electrode in a chamber, the chamber including the first electrode and a second electrode arranged to face each other, and etching the target. The etching the target includes applying a plurality of RF powers to one of the first and second electrodes. The plurality of RF powers may include a first RF power having a first frequency in a range from about 40 MHz to about 300 MHz, a second RF power having a second frequency in a range from about 100 kHz to about 10 MHz, and a third RF power having a third frequency in a range from about 10 kHz to about 5 MHz.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: July 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoyong Park, Namjun Kang, Dougyong Sung, Seungbo Shim, Junghyun Cho, Myungsun Choi
  • Patent number: 11075088
    Abstract: Disclosed are a method of plasma etching and a method of fabricating a semiconductor device including the same. The method of plasma etching includes loading a substrate including an etch target onto a first electrode in a chamber, the chamber including the first electrode and a second electrode arranged to face each other, and etching the target. The etching the target includes applying a plurality of RF powers to one of the first and second electrodes. The plurality of RF powers may include a first RF power having a first frequency in a range from about 40 MHz to about 300 MHz, a second RF power having a second frequency in a range from about 100 kHz to about 10 MHz, and a third RF power having a third frequency in a range from about 10 kHz to about 5 MHz.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: July 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoyong Park, Namjun Kang, Dougyong Sung, Seungbo Shim, Junghyun Cho, Myungsun Choi
  • Publication number: 20210213177
    Abstract: A substrate subject to degradation at temperatures above 100° C. is coated with a nanostructured ceramic coating having a thickness in excess of 100 nm, formed on a surface of the substrate, wherein a process temperature for deposition of the nanostructured coating does not exceed 90° C. The coating may be photocatalytic, photovoltaic, or piezoelectric. The coating, when moistened and exposed to ultraviolet light or sunlight, advantageously generates free radicals, which may be biocidal, deodorizing, or assist in degradation of surface deposits on the substrate after use. The substrate may be biological or organic, and may have a metallic or conductive intermediate layer.
    Type: Application
    Filed: November 9, 2020
    Publication date: July 15, 2021
    Inventor: Junghyun Cho
  • Patent number: 11062924
    Abstract: A semiconductor packaging apparatus and methods of manufacturing semiconductor devices using the same. The semiconductor packaging apparatus includes a process unit, and a controller associated with the process unit. The process unit includes a bonding part that bonds a semiconductor substrate and a carrier substrate to each other to form a bonded substrate, a cooling part that cools the bonded substrate, and a detection part in the cooling part and configured to detect a defect of the bonded substrate. The controller is configured to control the process unit using data obtained from the detection part.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghyun Cho, Sang-Geun Park, Dongseok Baek, Jaehyuk Choi
  • Publication number: 20210183618
    Abstract: Embodiments of the inventive concepts provide antennas, plasma generating circuits, plasma processing apparatus, and methods for manufacturing semiconductor devices using the same. The circuits include radio-frequency power sources generating radio-frequency powers, antennas receiving the radio-frequency powers to generate plasma and having a first mutual inductance, and inductors connecting the antennas to the radio-frequency power sources, respectively. The inductors have a second mutual inductance reducing and/or canceling the first mutual inductance.
    Type: Application
    Filed: February 26, 2021
    Publication date: June 17, 2021
    Inventors: Dong-Hyub LEE, Dougyong SUNG, Je-Hun WOO, Bongseong KIM, Juho LEE, Yun-Kwang JEON, Junghyun CHO
  • Publication number: 20210183950
    Abstract: A variable resistance memory device including a substrate; first and second transistors on the substrate; first conductive lines on the transistors, each of the first conductive lines extending in a first direction, and the first conductive lines being spaced apart from each other; first contact plugs directly contacting substrate-facing surfaces of the first conductive lines, the first contact plugs being electrically connected to the first transistors, respectively; second conductive lines on the first conductive lines, each of the second conductive lines extending in the second direction, and the second conductive lines being spaced apart from each other; second contact plugs directly contacting substrate-facing surfaces of the second conductive lines, the second contact plugs being electrically connected to the second transistors, respectively; and memory units between the conductive lines, wherein each of the second contact plugs does not overlap with any of the memory units in the third direction.
    Type: Application
    Filed: September 22, 2020
    Publication date: June 17, 2021
    Inventor: Junghyun CHO