Abstract: Memory devices may send information related to refresh rates to a memory controller. The memory controller may instruct the memory devices to refresh based on the received information.

Abstract: A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations. The memory controller keeps one or more non-conflicting pages open during the refresh operations.

Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.

Abstract: In a particular embodiment, a device includes memory address remapping circuitry and a remapping engine. The memory address remapping circuitry includes a comparison circuit to compare a received memory address to one or more remapped addresses. The memory address remapping circuitry also includes a selection circuit responsive to the comparison circuit to output a physical address. The physical address corresponds to a location in a random-access memory (RAM). The remapping engine is configured to update the one or more remapped addresses to include a particular address in response to detecting that a number of occurrences of errors at a particular location satisfies a threshold.

Abstract: A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.

Abstract: A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations. The memory controller keeps one or more non-conflicting pages open during the refresh operations.

Abstract: A memory refresh method within a memory controller includes checking a first retention state corresponding to a first memory address and a second retention state corresponding to a second memory address. The memory refresh method also includes performing a refresh operation on a row corresponding to the second memory address when the second retention state indicates a weak retention state. The first memory address corresponds to a refresh counter address, and the second memory address corresponds to a complementary address of the refresh counter address.

Abstract: An integrated circuit package is disclosed that includes a first-pitch die and a second-pitch die. The second-pitch die interconnects to the second-pitch substrate through second-pitch substrates. The first-pitch die interconnects through first-pitch interconnects to an interposer adapter. The pitch of the first-pitch interconnects is too fine for the second-pitch substrate. But the interposer adapter interconnects through second-pitch interconnects to the second-pitch substrate and includes through substrate vias so that I/O signaling between the first-pitch die and the second-pitch die can be conducted through the second-pitch substrate and through the through substrate vias in the interposer adapter.

Abstract: A particular method includes receiving, from a processor, a first memory access request at a memory device. The method also includes processing the first memory access request based on a timing parameter of the memory device. The method further includes receiving, from the processor, a second memory access request at the memory device. The method also includes modifying a timing parameter of the memory device based on addresses identified by the first memory access request and the second memory access request to produce a modified timing parameter. The method further includes processing the second memory access request based on the modified timing parameter.

Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.

Abstract: Methods and apparatus for a providing temperature-compensated reference voltage are provided. In an example, a temperature-compensated voltage reference circuit includes a current mirror portion and a temperature-compensated output portion coupled to the current mirror portion. The temperature-compensated output portion comprises a very low threshold voltage (Vt) transistor coupled in series with a negative temperature coefficient transistor. The output portion can further include a positive temperature coefficient element coupled in series with the very low Vt transistor. The positive temperature coefficient element can be an adjustable resistive element. The output portion can further include an output transistor having a gate coupled to the current mirror portion and coupled between a supply voltage and the positive temperature coefficient element. The very low Vt transistor can be a substantially zero Vt n-channel metal-oxide-semiconductor (NMOS) transistor, and can be coupled in a diode configuration.

Abstract: Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage.

Abstract: Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability.

Abstract: A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

Abstract: A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.

Abstract: A resistance-based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line and a sense line to generate a current through a resistance-based memory element via a first diode or a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.

Abstract: Apparatuses and methods for low power combined self-refresh and self-correction of a Dynamic Random Access Memory (DRAM) array. During a self-refresh cycle, a first portion of a first row of the DRAM array is accessed and analyzed for one or more errors, wherein a bit width of the first portion is less than a bit width of the first row. If one or more errors are detected, the one or more errors are corrected to form a corrected first portion. The corrected first portion is selectively written back to the first row. If no errors are detected in the first portion, a write back of the first portion to the first row is prevented.

Abstract: In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.

Abstract: A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.