Patents by Inventor Junji Kotani
Junji Kotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240297246Abstract: A semiconductor device includes an AlN substrate, a semiconductor laminated structure, disposed above the substrate, and including an electron transit layer and an electron supply layer made of a nitride semiconductor, respectively, and a gate electrode, a source electrode, and a drain electrode disposed above the electron supply layer. The electron transit layer is located at a lowermost position of the semiconductor laminated structure. The gate electrode has a gate length of 0.3 ?m or less, and a ratio of a thickness of the semiconductor laminated structure with respect to the gate length of the gate electrode is 4.0 or less.Type: ApplicationFiled: April 26, 2024Publication date: September 5, 2024Applicant: FUJITSU LIMITEDInventors: Shirou OZAKI, Junji KOTANI, Atsushi YAMADA
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Patent number: 11791384Abstract: A semiconductor device includes an underlayer made of a first nitride semiconductor, a first buffer layer made of a second nitride semiconductor, provided on the underlayer, and subjected to compressive stress from the underlayer in an in-plane direction which is perpendicular to a thickness direction of the underlayer, a second buffer layer made of a third nitride semiconductor, provided on the first buffer layer, and subjected to compressive stress from the first buffer layer in the in-plane direction, a channel layer made of a fourth nitride semiconductor, provided on the second buffer layer, and subjected to compressive stress from the second buffer layer in the in-plane direction, and a barrier layer made of a fifth nitride semiconductor, and provided above the channel layer.Type: GrantFiled: March 23, 2021Date of Patent: October 17, 2023Assignee: FUJITSU LIMITEDInventors: Junya Yaita, Junji Kotani, Atsushi Yamada, Kozo Makiyama
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Patent number: 11646366Abstract: A disclosed semiconductor device includes an electron transit layer; an electron supply layer disposed above the electron transit layer; a source electrode, a drain electrode, and a gate electrode, the source electrode, the drain electrode, and the gate electrode being disposed on the electron supply layer; a first capping layer disposed on the electron supply layer between the gate electrode and the drain electrode; and a negative charge generation layer disposed on the first capping layer, the negative charge generation layer being configured to generate a negative charge.Type: GrantFiled: December 21, 2020Date of Patent: May 9, 2023Assignee: FUJITSU LIMITEDInventors: Kozo Makiyama, Shirou Ozaki, Atsushi Yamada, Junji Kotani
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COMPOUND SEMICONDUCTOR DEVICE, AMPLIFIER, AND METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE
Publication number: 20230037148Abstract: A compound semiconductor device includes a carrier supply layer, a channel layer disposed over the carrier supply layer and configured to include InGaAs, and an etching stopper layer disposed over the channel layer, and configured to include a first layer disposed over the channel layer and configured to include Inx1Ga1-x1P, and a second layer disposed over the first layer and configured to include Inx2Ga1-x2P, wherein x1 is greater than 0 and less than or equal to 1, x2 is greater than or equal to 0 and less than 1, and x1 is greater than x2.Type: ApplicationFiled: April 25, 2022Publication date: February 2, 2023Applicant: FUJITSU LIMITEDInventors: Shirou OZAKI, Junji KOTANI, Toshihiro OHKI, Naoya OKAMOTO -
Publication number: 20220190151Abstract: A semiconductor device is provided. In particular, a semiconductor device is disclosed as including an electron transit layer; an electron supply layer disposed on or above the electron transit layer, the electron supply layer inducing a two-dimensional electron gas in the electron transit layer; a source electrode disposed on or above the electron supply layer; a drain electrode disposed on or above the electron supply layer; a gate electrode between the source electrode and the drain electrode; and an insulating film that is disposed in a region between the gate electrode and the drain electrode, and the region being closer to the gate electrode than to the drain electrode. The insulating film includes a nitrosyl group.Type: ApplicationFiled: September 22, 2021Publication date: June 16, 2022Applicant: FUJITSU LIMITEDInventors: Shirou Ozaki, Junji Kotani
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Publication number: 20220069112Abstract: A semiconductor device includes an AlN substrate, a semiconductor laminated structure, disposed above the substrate, and including an electron transit layer and an electron supply layer made of a nitride semiconductor, respectively, and a gate electrode, a source electrode, and a drain electrode disposed above the electron supply layer. The electron transit layer is located at a lowermost position of the semiconductor laminated structure. The gate electrode has a gate length of 0.3 ?m or less, and a ratio of a thickness of the semiconductor laminated structure with respect to the gate length of the gate electrode is 4.0 or less.Type: ApplicationFiled: April 12, 2021Publication date: March 3, 2022Applicant: FUJITSU LIMITEDInventors: Shirou OZAKI, Junji KOTANI, Atsushi YAMADA
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Publication number: 20220013642Abstract: A semiconductor device includes an underlayer made of a first nitride semiconductor, a first buffer layer made of a second nitride semiconductor, provided on the underlayer, and subjected to compressive stress from the underlayer in an in-plane direction which is perpendicular to a thickness direction of the underlayer, a second buffer layer made of a third nitride semiconductor, provided on the first buffer layer, and subjected to compressive stress from the first buffer layer in the in-plane direction, a channel layer made of a fourth nitride semiconductor, provided on the second buffer layer, and subjected to compressive stress from the second buffer layer in the in-plane direction, and a barrier layer made of a fifth nitride semiconductor, and provided above the channel layer.Type: ApplicationFiled: March 23, 2021Publication date: January 13, 2022Applicant: FUJITSU LIMITEDInventors: Junya YAITA, Junji KOTANI, Atsushi YAMADA, Kozo MAKIYAMA
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Patent number: 11194234Abstract: A projector includes a communication unit configured to communicate with an external device, an operation unit configured to receive a user operation, and a system control unit. The system control unit is configured to validate a network function of the communication unit in response to receipt of a particular key sequence received by the operation unit in a stand-by state. The system control unit is configured not to validate the network function of the communication unit even if the operation unit receives the particular key sequence in an image projection state.Type: GrantFiled: December 9, 2020Date of Patent: December 7, 2021Assignee: CANON KABUSHIKI KAISHAInventors: Junji Kotani, Masato Yoshioka
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Publication number: 20210234031Abstract: A disclosed semiconductor device includes an electron transit layer; an electron supply layer disposed above the electron transit layer; a source electrode, a drain electrode, and a gate electrode, the source electrode, the drain electrode, and the gate electrode being disposed on the electron supply layer; a first capping layer disposed on the electron supply layer between the gate electrode and the drain electrode; and a negative charge generation layer disposed on the first capping layer, the negative charge generation layer being configured to generate a negative charge.Type: ApplicationFiled: December 21, 2020Publication date: July 29, 2021Applicant: FUJITSU LIMITEDInventors: Kozo MAKIYAMA, Shirou OZAKI, Atsushi YAMADA, Junji KOTANI
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Publication number: 20210191238Abstract: A projector includes a communication unit configured to communicate with an external device, an operation unit configured to receive a user operation, and a system control unit. The system control unit is configured to validate a network function of the communication unit in response to receipt of a particular key sequence received by the operation unit in a stand-by state. The system control unit is configured not to validate the network function of the communication unit even if the operation unit receives the particular key sequence in an image projection state.Type: ApplicationFiled: December 9, 2020Publication date: June 24, 2021Inventors: Junji Kotani, Masato Yoshioka
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Patent number: 10992269Abstract: A compound semiconductor device includes a first compound semiconductor layer containing a p-type impurity, a second compound semiconductor layer disposed over the first compound semiconductor layer and containing InGaN, an electron transit layer disposed over the second compound semiconductor layer, and an electron supply layer disposed over the electron transit layer.Type: GrantFiled: July 11, 2018Date of Patent: April 27, 2021Assignee: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Atsushi Yamada, Junji Kotani, Norikazu Nakamura, Kozo Makiyama
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Patent number: 10847642Abstract: Disclosed is a compound semiconductor device that includes an electron transit layer; an electron supply layer disposed above the electron transit layer, and including a first region and a second region, the second region having a composition higher in Al than the first region and covering the first region from at least a bottom part of the second region; a first electrode disposed above the first region; and a second electrode disposed above the second region.Type: GrantFiled: June 21, 2018Date of Patent: November 24, 2020Assignee: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Junji Kotani, Norikazu Nakamura
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Publication number: 20200335615Abstract: A semiconductor device includes a substrate that contains a first nitride semiconductor, an uneven layer that is provided on the substrate, contains a second nitride semiconductor, and has unevenness in a surface, a channel layer that is provided on the uneven layer and contains a third nitride semiconductor, a barrier layer that is provided on the channel layer and contains a fourth nitride semiconductor, wherein, in the uneven layer, an area of a portion that falls within a range within a mode value±1 nm of a position of the surface in a height direction falls within a range of 46% to 75% with respect to an area of the entire surface.Type: ApplicationFiled: March 12, 2020Publication date: October 22, 2020Applicant: FUJITSU LIMITEDInventors: Atsushi Yamada, JUNJI KOTANI
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Patent number: 10768884Abstract: A communication apparatus that is capable of communicating with one of a plurality of display apparatuses, so that an integrated image screen is constituted by combining display image screens of the plurality of display apparatuses, comprises at least one processor or circuit to perform the operations of the following units: a detection unit configured to detect, among the plurality of display apparatuses, a display apparatus that is close to the communication apparatus within a predetermined range to establish near field wireless communication; and a display unit configured to display information relating to, of the plurality of display apparatuses, a first display apparatus to which the communication apparatus is to be brought close so that the first display apparatus is detected by that detection unit.Type: GrantFiled: November 16, 2018Date of Patent: September 8, 2020Assignee: Canon Kabushiki KaishaInventor: Junji Kotani
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Patent number: 10707338Abstract: A semiconductor device includes a substrate; a first barrier layer containing AlN, over the substrate; a channel layer containing BGaN, over the first barrier layer; and a second barrier layer containing AlN, over the channel layer. A difference between a first lattice constant of the channel layer and a second lattice constant of the first barrier layer is less than or equal to 1.55% of the second lattice constant.Type: GrantFiled: February 25, 2019Date of Patent: July 7, 2020Assignee: FUJITSU LIMITEDInventors: Atsushi Yamada, Junji Kotani
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Projection apparatus, method for controlling projection apparatus, and non-transitory storage medium
Patent number: 10681320Abstract: One or more projection apparatuses, control methods for one or more projection apparatuses, and storage mediums for use therewith are provided herein. At least one projection apparatus includes: a projection unit including an optical unit, the projection unit being configured to project a projection image including a predetermined display item onto a projection surface; a sensor configured to sense a predetermined area corresponding to the predetermined display item on the projection surface; and a control unit configured to: (i) perform predetermined processing relating to the projection image in response to the sensor detecting a predetermined instruction in the predetermined area, and (ii) stop sensing performed by the sensor in a case where a state of the optical system of the projection unit changes while the projection image including the predetermined display item is being projected.Type: GrantFiled: May 25, 2018Date of Patent: June 9, 2020Assignee: Canon Kabushiki KaishaInventors: Junji Kotani, Hidetoshi Wada -
Patent number: 10665710Abstract: A disclosed compound semiconductor device includes a channel layer configured to generate carriers; a spacer layer of Aly1Ga1-y1N (0.20<y1?0.70) formed on the channel layer; and a barrier layer of Inx2Aly2 Ga1-x2-y2N (0?x2?0.15 and 0.20?y2<0.70) formed on the spacer layer, where y1 and y2 satisfy a relationship of y1>y2.Type: GrantFiled: January 2, 2019Date of Patent: May 26, 2020Assignee: FUJITSU LIMITEDInventors: Atsushi Yamada, Junji Kotani
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Patent number: 10651305Abstract: A compound semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, a channel layer formed over the compound semiconductor layer, an electron supply layer formed over the channel layer, and a source electrode, a drain electrode, and a gate electrode that are formed apart from each other over the electron supply layer. A quantum well structure is formed by the compound semiconductor layer, the channel layer, and the electron supply layer.Type: GrantFiled: July 26, 2018Date of Patent: May 12, 2020Assignee: FUJITSU LIMITEDInventors: Junji Kotani, Norikazu Nakamura, Hisao Shigematsu
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Patent number: 10630947Abstract: A projection apparatus that is capable of reducing difference in color tones between diffused light with a high diffusion degree and non-diffused light with a low diffusion degree. An irradiation unit irradiates with light including color components. A modulation unit modulates the light irradiated by the irradiation unit. A diffusion unit diffuses and outputs the light incident from the modulation unit. A color setting unit sets up a target color of the light output from the diffusion unit. A controller controls the irradiation unit and the modulation unit. The controller controls at least one of the irradiation unit and the modulation unit according to variation of characteristics of the diffusion unit so that difference between a color of the light diffused by the diffusion unit and the target color will become small.Type: GrantFiled: September 4, 2018Date of Patent: April 21, 2020Assignee: CANON KABUSHIKI KAISHAInventor: Junji Kotani
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Patent number: 10622469Abstract: A compound semiconductor device includes an electron transit layer, a spacer layer disposed on the electron transit layer, and an electron supply layer disposed on the spacer layer and containing a donor impurity. The electron supply layer has a concentration distribution of the donor impurity where the donor impurity is at a first concentration at an interface between the electron supply layer and the spacer layer and at a second concentration lower than the first concentration at an upper surface of the electron supply layer, and a concentration of the donor impurity at one of arbitrarily-selected two positions closer to the upper surface in a thickness direction of the electron supply layer is less than the concentration of the donor impurity at another one of the two positions closer to the interface in the thickness direction.Type: GrantFiled: May 10, 2018Date of Patent: April 14, 2020Assignee: FUJITSU LIMITEDInventors: Junji Kotani, Norikazu Nakamura