Patents by Inventor Junji Kotani

Junji Kotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9831310
    Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure including a first buffer layer composed of AlN; and a second buffer layer composed of AlGaN and formed above the first buffer layer, wherein the second buffer layer contains carbon, and wherein the concentration of carbon in the second buffer layer increases with increasing distance from a lower surface of the second buffer layer toward an upper surface of the second buffer layer.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: November 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura
  • Publication number: 20170222016
    Abstract: A compound semiconductor device includes: a semiconductor substrate; a channel layer over the semiconductor substrate; a carrier supply layer over the channel layer; and a gate electrode, a source electrode and a drain electrode above the carrier supply layer. The semiconductor substrate includes an impurity-containing region containing an impurity, the impurity forms a level lower than a lower edge of a conduction band of silicon by 0.25 eV or more, the impurity forms the level higher than an upper edge of a valence band of silicon.
    Type: Application
    Filed: April 14, 2017
    Publication date: August 3, 2017
    Applicant: FUJITSU LIMITED
    Inventor: JUNJI KOTANI
  • Patent number: 9691890
    Abstract: A compound semiconductor device includes a compound semiconductor stacked structure, the compound semiconductor stacked structure including: an electron transit layer; an electron supply layer formed above the electron transit layer, the electron supply layer containing an n-type impurity; and a cap layer formed above the electron supply layer and containing the n-type impurity, in which in the electron supply layer, a concentration of the n-type impurity contained therein is non-uniform in a film thickness direction and a concentration of the n-type impurity in a surface of the cap layer side is lower than a maximum concentration of the n-type impurity in the electron supply layer.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: June 27, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Norikazu Nakamura, Atsushi Yamada, Junji Kotani
  • Patent number: 9653590
    Abstract: A compound semiconductor device includes: a semiconductor substrate; a channel layer over the semiconductor substrate; a carrier supply layer over the channel layer; and a gate electrode, a source electrode and a drain electrode above the carrier supply layer. The semiconductor substrate includes an impurity-containing region containing an impurity, the impurity forms a level lower than a lower edge of a conduction band of silicon by 0.25 eV or more, the impurity forms the level higher than an upper edge of a valence band of silicon.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: May 16, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Junji Kotani
  • Publication number: 20170125533
    Abstract: A semiconductor apparatus includes a semiconductor chip including a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, and a gate electrode, a source electrode, and a drain electrode formed over the second semiconductor layer. The gate electrode is formed in a comb shape having a plurality of tooth parts. An interval between the tooth parts becomes narrower from a center part toward a peripheral part of the semiconductor chip. The source electrode is formed on one of two sides of each of the tooth parts in the gate electrode, and the drain electrode is formed on another of the two sides. The source electrodes and the drain electrodes formed between the tooth parts in the gate electrode have respective areas that are substantially the same in a plan view.
    Type: Application
    Filed: September 8, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: JUNJI KOTANI, NORIKAZU NAKAMURA
  • Publication number: 20170125566
    Abstract: A compound semiconductor device includes a compound semiconductor stacked structure, the compound semiconductor stacked structure including: an electron transit layer; an electron supply layer formed above the electron transit layer, the electron supply layer containing an n-type impurity; and a cap layer formed above the electron supply layer and containing the n-type impurity, in which in the electron supply layer, a concentration of the n-type impurity contained therein is non-uniform in a film thickness direction and a concentration of the n-type impurity in a surface of the cap layer side is lower than a maximum concentration of the n-type impurity in the electron supply layer.
    Type: Application
    Filed: October 3, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: NORIKAZU NAKAMURA, ATSUSHI YAMADA, JUNJI KOTANI
  • Publication number: 20170125564
    Abstract: A semiconductor crystal substrate includes a substrate, a first semiconductor layer including a nitride semiconductor and formed over the substrate, a second semiconductor layer including a nitride semiconductor and formed over the first semiconductor layer, a first cap layer formed on the second semiconductor layer, and a second cap layer formed on the first cap layer. Each of the first semiconductor layer and the second semiconductor layer has a single-crystal structure, the first cap layer has one of a single-crystal structure and a polycrystalline structure, and the second cap layer has an amorphous structure.
    Type: Application
    Filed: September 26, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: JUNJI KOTANI, NORIKAZU NAKAMURA
  • Patent number: 9548365
    Abstract: A semiconductor device includes: a buffer layer formed over a substrate; a first semiconductor layer formed over the buffer layer by using a compound semiconductor; a second semiconductor layer formed over the first semiconductor layer by using a compound semiconductor; and a gate electrode, a source electrode, and a drain electrode formed over the second semiconductor layer, wherein the first semiconductor layer contains an impurity element serving as an acceptor and an impurity element serving as a donor; and in the first semiconductor layer, an acceptor concentration of the impurity element serving as the acceptor is greater than a donor concentration of the impurity element serving as the donor; and the donor concentration is greater-than over equal to 5×1016 cm?3.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: January 17, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura
  • Publication number: 20160359032
    Abstract: A compound semiconductor device includes: a carrier transit layer; a carrier supply layer that is formed over the carrier transit layer and is made of InAlN; and a spacer layer that is formed between the carrier transit layer and the carrier supply layer and is made of at least one of AlGaN and InAlGaN.
    Type: Application
    Filed: May 31, 2016
    Publication date: December 8, 2016
    Applicant: FUJITSU LIMITED
    Inventors: JUNJI KOTANI, NORIKAZU NAKAMURA, Tetsuro Ishiguro
  • Publication number: 20160172478
    Abstract: A semiconductor device includes: a buffer layer formed over a substrate; a first semiconductor layer formed over the buffer layer by using a compound semiconductor; a second semiconductor layer formed over the first semiconductor layer by using a compound semiconductor; and a gate electrode, a source electrode, and a drain electrode formed over the second semiconductor layer, wherein the first semiconductor layer contains an impurity element serving as an acceptor and an impurity element serving as a donor; and in the first semiconductor layer, an acceptor concentration of the impurity element serving as the acceptor is greater than a donor concentration of the impurity element serving as the donor; and the donor concentration is greater-than over equal to 5×1016 cm?3.
    Type: Application
    Filed: October 26, 2015
    Publication date: June 16, 2016
    Applicant: FUJITSU LIMITED
    Inventors: JUNJI KOTANI, NORIKAZU NAKAMURA
  • Patent number: 9350898
    Abstract: An apparatus control method includes receiving an image, displaying the received image, presenting candidates for a printing device to be allowed to print the displayed image, selecting at least one of the presented candidates for the printing device, and transmitting, to the selected printing device, an instruction to print the displayed image. When the candidates for the printing device include a printing device that transmitted the image, the printing device that transmitted the image is presented in preference to the other printing devices.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 24, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Junji Kotani
  • Publication number: 20150381850
    Abstract: An apparatus control method includes receiving an image, displaying the received image, presenting candidates for a printing device to be allowed to print the displayed image, selecting at least one of the presented candidates for the printing device, and transmitting, to the selected printing device, an instruction to print the displayed image. When the candidates for the printing device include a printing device that transmitted the image, the printing device that transmitted the image is presented in preference to the other printing devices.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 31, 2015
    Inventor: Junji Kotani
  • Publication number: 20150372125
    Abstract: A compound semiconductor device includes: a semiconductor substrate; a channel layer over the semiconductor substrate; a carrier supply layer over the channel layer; and a gate electrode, a source electrode and a drain electrode above the carrier supply layer. The semiconductor substrate includes an impurity-containing region containing an impurity, the impurity forms a level lower than a lower edge of a conduction band of silicon by 0.25 eV or more, the impurity forms the level higher than an upper edge of a valence band of silicon.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 24, 2015
    Inventor: JUNJI KOTANI
  • Patent number: 9196685
    Abstract: A semiconductor device includes a first superlattice buffer layer formed on a substrate. A second superlattice buffer layer is formed on the first superlattice buffer layer. A first semiconductor layer is formed by a nitride semiconductor on the second superlattice buffer layer. A second semiconductor layer is formed by a nitride semiconductor on the first semiconductor layer. The first superlattice buffer layer is formed by alternately and cyclically laminating a first superlattice formation layer and a second superlattice formation layer. The second superlattice buffer layer is formed by alternately and cyclically laminating the first superlattice formation layer and the second superlattice formation layer. The first superlattice formation layer is formed by AlxGa1-xN, and the second superlattice formation layer is formed by AyGa1-yN, where x>y. A concentration of an impurity element doped into the second superlattice buffer layer is higher than that doped into the first superlattice buffer layer.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: November 24, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Shuichi Tomabechi, Junji Kotani
  • Patent number: 9166031
    Abstract: A semiconductor device includes a superlattice buffer layer formed on a substrate. A first semiconductor layer is formed by a nitride semiconductor on the superlattice buffer layer. A second semiconductor layer is formed by a nitride semiconductor on the first semiconductor layer. A gate electrode, a source electrode and a drain electrode are formed on the second semiconductor layer. The superlattice buffer layer is formed by alternately and periodically laminating a first superlattice formation layer and a second superlattice formation layer. The first superlattice formation layer is formed by AlxGa1-xN and the second superlattice formation layer is formed by AlyGa1-yN, where a relationship x>y is satisfied. A concentration of an impurity element serving as an acceptor doped into a portion or a whole of the second superlattice formation layer is higher than a concentration of the impurity element serving as an acceptor doped into the first superlattice formation layer.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: October 20, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura
  • Patent number: 9082330
    Abstract: An information processor receives, from each of a plurality of projectors, the number of pixels to be projected and the number of pixels of a region to be superposed of the projector, and the information processor calculates the number of pixels of an integrated image based on the number of pixels to be projected and the number of pixels of a region to be superposed of each projection screen of the projectors.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: July 14, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Junji Kotani
  • Patent number: 9070757
    Abstract: A semiconductor device includes a superlattice buffer layer formed on a substrate. A first semiconductor layer is formed by a nitride semiconductor on the superlattice buffer layer. A second semiconductor layer is formed by a nitride semiconductor on the first semiconductor layer. A gate electrode, a source electrode and a drain electrode are formed on the second semiconductor layer. The superlattice buffer layer is formed by alternately and periodically laminating a first superlattice formation layer and a second superlattice formation layer. The first superlattice formation layer is formed by AlxGa1-xN and the second superlattice formation layer is formed by AlyGa1-yN, where a relationship x>y is satisfied. A concentration of an impurity element serving as an acceptor doped into a portion or a whole of the second superlattice formation layer is higher than a concentration of the impurity element serving as an acceptor doped into the first superlattice formation layer.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: June 30, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura
  • Patent number: 9029868
    Abstract: A semiconductor apparatus includes a substrate; a buffer layer formed on the substrate; a first semiconductor layer formed on the buffer layer; and a second semiconductor layer formed on the first semiconductor layer. Further, the buffer layer is formed of AlGaN and doped with Fe, the buffer layer includes a plurality of layers having different Al component ratios from each other, and the Al component ratio of a first layer is greater than the Al component ratio of a second layer and a Fe concentration of the first layer is less than the Fe concentration of the second layer, the first and second layers being included in the plurality of layers, and the first layer being formed on a substrate side of the second layer.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventors: Junji Kotani, Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura
  • Patent number: 9024358
    Abstract: A compound semiconductor device includes a substrate; a buffer layer formed on the substrate; an electron transit layer and an electron donating layer formed on the buffer layer; a gate electrode, a source electrode, and a drain electrode formed on the electron donating layer; and an embedded electrode to which a potential independent of the gate electrode, the source electrode, and the drain electrode is supplied to control a potential of the buffer layer.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: May 5, 2015
    Assignee: Fujitsu Limited
    Inventor: Junji Kotani
  • Publication number: 20150090957
    Abstract: A semiconductor device includes a first superlattice buffer layer formed on a substrate. A second superlattice buffer layer is formed on the first superlattice buffer layer. A first semiconductor layer is formed by a nitride semiconductor on the second superlattice buffer layer. A second semiconductor layer is formed by a nitride semiconductor on the first semiconductor layer. The first superlattice buffer layer is formed by alternately and cyclically laminating a first superlattice formation layer and a second superlattice formation layer. The second superlattice buffer layer is formed by alternately and cyclically laminating the first superlattice formation layer and the second superlattice formation layer. The first superlattice formation layer is formed by AlxGa1-xN, and the second superlattice formation layer is formed by AyGa1-yN, where x>y. A concentration of an impurity element doped into the second superlattice buffer layer is higher than that doped into the first superlattice buffer layer.
    Type: Application
    Filed: July 7, 2014
    Publication date: April 2, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Shuichi TOMABECHI, JUNJI KOTANI