Abstract: A plant mowing apparatus in which a driven case is rotationally engaged by way of a braking device to a cylindrical frame having a rotary driving shaft pivoted therein and a plurality of cutter rotary shafts each having rotary blade units joined at the top end is attached to the driven case in parallel with the rotary driving shaft, rotary bodies having predetermined circumferential ratio are fixed respectively, to the rotary driving shaft and the cutter rotary driving shaft, and the rotary body for the cutter rotary shaft and the rotary body for the rotary driving shaft are connected by way of a rotation transmitting unit, such that the cutter rotary shaft revolves under auto-rotation. The cutter unit of the rotary blade having a plurality of blade edges at the circumferential side and each of the blade edges is turned to the rotational direction for cutting by the change of the attaching angle, the rotary blade unit and the cutter rotary shaft are engaged under pressure by way of a resilient member.

Abstract: A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.

Abstract: A restoring circuit 24, provided for each of the memory blocks 191 and 192, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder 26. The present row address is held in one of the registers. When amplification is started by a sense amplifier 15, transfer gates 10 and 11 connected between the bit lines BL1 and *BL1 and the sense amplifier 15 are turned off to decrease the load of the sense amplifier 15, the amplified signal is stored in a buffer memory cell circuit 18, and accessing is completed with omitting restoring to the memory cell 12. While the memory cell block 191 is not selected, the data held in the buffer memory cell circuit 18 is stored into the memory cell row addressed by the content of the selected register. The sense amplifier 15 has PMOS and NMOS sense amplifiers.

Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Abstract: A restoring circuit 24, provided for each of the memory blocks 191 and 192, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder 26. The present row address is held in one of the registers. When amplification is started by a sense amplifier 15, transfer gates 10 and 11 connected between the bit lines BL1 and *BL1 and the sense amplifier 15 are turned off to decrease the load of the sense amplifier 15, the amplified signal is stored in a buffer memory cell circuit 18, and accessing is completed with omitting restoring to the memory cell 12. While the memory cell block 191 is not selected, the data held in the buffer memory cell circuit 18 is stored into the memory cell row addressed by the content of the selected register. The sense amplifier 15 has PMOS and NMOS sense amplifiers.

Abstract: A restoring circuit 24, provided for each of the memory blocks 191 and 192, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder 26. The present row address is held in one of the registers. When amplification is started by a sense amplifier 15, transfer gates 10 and 11 connected between the bit lines BL1 and *BL1 and the sense amplifier 15 are turned off to decrease the load of the sense amplifier 15, the amplified signal is stored in a buffer memory cell circuit 18, and accessing is completed with omitting restoring to the memory cell 12. While the memory cell block 191 is not selected, the data held in the buffer memory cell circuit 18 is stored into the memory cell row addressed by the content of the selected register. The sense amplifier 15 has PMOS and NMOS sense amplifiers.

Abstract: A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when the signal transmission line is switched between the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle-time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.

Abstract: A phase-locked loop circuit is constituted in such a manner that a delayed signal created by causing an input signal to loop through a delay stage a plurality of times is compared in terms of phase with the input signal, and an amount of delay in the delay stage is controlled in accordance with the comparison result of the delayed signal and the input signal. Therefore, the circuit size can be reduced with a reduced number of delay units constituting the delay stage.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: A television channel selection monitoring apparatus for identifying the broadcast channel to which a television receiver means is tuned at any given time is disclosed. Instead of relying for the channel identification on the local oscillation frequency at the tuner of such television receiver means, the apparatus of the present invention utilizes the recognition of the channel identification number superimposed on the video signal received through the selected channel so that the image of the superimposed channel number may appear, for a certain duration following the channel selection, at a predetermined area of the image corresponding to the video signal.

Abstract: A semiconductor integrated circuit device includes a flat-range voltage supply unit which steps down an external power supply voltage and generates a resultant, flat-range voltage, and a burn-in voltage supply unit which generates a burn-in voltage depending on the external power supply voltage. A switching unit selects either the flat-range voltage or the burn-in voltage, a selected voltage being supplied to an internal circuit. A switching instruction unit includes switches and generates a switching instruction signal by an ON/OFF control of the switches. A switching control unit controls the switching unit in accordance with the switching instruction signal.

Abstract: A memory device has a plurality of word lines, a plurality of bit lines crossing the word lines, and a memory cell array having memory cells disposed at respective points of intersection between the word lines and the bit lines. The memory device includes a first redundant memory cell array, a first address comparison circuit, a second redundant memory cell array, and a second address comparison circuit. The first redundant memory cell array replaces memory cells with redundant memory cells per bit or a small number of bits. The first address comparison circuit stores an addresses of memory cells to be replaced, compares the stored addresses with an inputted address, and allows a memory cell to be replaced effectively with a redundant memory cell in the first redundant memory cell array when a stored address matches the inputted address. The second redundant memory cell array replaces memory cells with redundant memory cells per word line or bit line.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: A semiconductor includes a Lead-on-chip (LOC) structure. A bonding pad solely for receiving a signal is formed parallel to a perimeter on top in the middle of the element-formation surface. A bonding pad solely for transmitting a signal is formed around the periphery of the element-formation surface, and an inner lead solely for receiving a signal has its tip positioned parallel to the perimeter on top in the middle of the element-formation surface. An inner lead solely for transmitting a signal has its tip positioned on top of the periphery of the element-formation surface.

Abstract: A semiconductor memory device enables multi-direction data access at a high speed with a simple circuit construction. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells connected to the bit lines and word lines. A row decoder, connected to the word lines, selects one of the word lines in response to a row address signal. A selection circuit includes a plurality of column decoders and a direction decoder. Each column decoder receives a portion of a column address signal and the direction decoder selects one of three directions in response to a direction address signal. Each column decoder is selectively enabled based upon the direction address signal. Output circuitry outputs data read out from bit lines selected by the enabled column decoders. Thus, three-dimensional bit map data can be stored in two dimensions.

Abstract: A semiconductor memory device enables multi-direction data access at a high speed with a simple circuit construction. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells connected to the bit lines and word lines. A row decoder, connected to the word lines, selects one of the word lines in response to a row address signal. A selection circuit includes a plurality of column decoders and a direction decoder. Each column decoder receives a portion of a column address signal and the direction decoder selects one of three directions in response to a direction address signal. Each column decoder is selectively enabled based upon the direction address signal. Output circuitry outputs data read out from bit lines selected by the enabled column decoders. Thus, three-dimensional bit map data can be stored in two dimensions.

Abstract: An image recognition apparatus includes a light source including a plurality of light emitting diodes having different wavelengths, for illuminating an object, a driver for selectively operating the light emitting diodes and adjusting the brightness thereof, an image pick-up device for photoelectrically transferring the light reflected from the object into an image signal, and an image decision device for comparing a reference image signal with the image signal obtained by the image pick-up device and then deciding whether an image corresponding to the obtained image signal is clearer than an image corresponding to the reference image signal, the image decision device making the driver sequentially operates the light emitting diodes and change the brightness thereof in such a manner that the image corresponding to the image signal is clearer than the image corresponding to the reference image signal.

Abstract: A laser therapeutic apparatus having an oscillator for generating a laser beam, a condenser lens for condensing the laser beam radiated from the oscillator, a plurality of optical fiber cables for guiding the condensed laser beam, and a probe connected to the distal end of each of the optical fiber cables to apply the laser beam to an affected part of a human body. The probe may be detachably connected to the distal end of the optical fiber through an optical connector. A plurality of optical fibers may have their respective laser beam emergent ends dispersedly disposed over the distal end portion of a probe casing constituting the probe. There may be prepared detachable cap-shaped attachments having various sizes which are conformable with various affected parts of patients, and a selected one of the attachments may be attached to the distal end portion of the probe casing. Thus, it is possible to carry out laser therapy efficiently and effectively.