Abstract: Optimal performance tuning is enabled by avoiding the deterioration in the performance of a storage system caused by an erroneous setting in a tuning parameter. The storage system has a primary volume provided as an operational volume to a host computer, and a secondary volume capable of forming a copy-pair with the primary volume. When the load demanded in executing I/O processing to the secondary volume set with a second tuning parameter is lighter than the load demanded in executing I/O processing to the primary volume set with a first tuning parameter, the storage controller switches the primary/secondary relationship between the primary volume and secondary volume and provides the secondary volume as the operational volume to the host computer.

Abstract: A storage device according to the present invention has a first volume for storing discontinuous data transmitted from a host computer and a second volume for storing continuous data produced by address-converting discontinuous data, and includes: a data storing unit for converting the discontinuous data transmitted from the host computer into the continuous data and storing the continuous data in one of a plurality of third volumes formed by dividing up the second volume; a data management unit for managing transfer target data that has to be transferred from the third to the first volume, from among the discontinuous data stored in the third volume by the data storing unit; and a volume clearance unit for clearing the third volume having the smallest amount of transfer target data managed by the data management unit by transferring the transfer target data in the relevant third volume to the first volume.

Abstract: The present invention enables to update a program in a storage control device while processing access requests, without imposing any burden on a host. When execution of updating of a program is commanded from a management terminal, an update control unit starts within the controller which is the object of updating. After a host I/F unit has been connected to an access request processing unit within another controller by a connection control unit, the update control unit updates a program which is stored in a program memory or a boot disk. When this updating is completed, the update control unit reconnects the host I/F unit to its access processing unit by the connection control unit. Since the stored contents of data memories are synchronized, the other access request processing unit can continue processing access requests from the host in place one access request processing unit.

Abstract: A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when the signal transmission line is switched between the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched.

Abstract: In order to provide a timing adjustment circuit capable of transmitting/receiving data without being affected by process unevenness and power voltage/temperature fluctuations even at a high data transfer rate, the phase of data outputted by a data transmitting unit is compared with the phase of a clock for regulating a data receiving timing of a data receiving unit, and the phase of a clock for regulating a data transmitting timing of the data transmitting unit is adjusted according to the comparison result.

Abstract: A clock distribution circuit for suitably generating, transmitting, and receiving clock signals used in circuits that are configured with the same circuit topology is provided. The clock distribution circuit has a transmission buffer circuit that transmits a clock signal and an amplitude amplification buffer circuit that amplifies the amplitude of cross-coupling connections inserted in parallel with the transmission buffer circuit on a transmission path for the clock signal. Wherein the number of transistors having the same conductivity type as the transistors of a differing conductivity type of the transmission buffer circuit and that of the transistors of a differing conductivity type of the amplitude amplification buffer circuit are the same. At least one transistor is provided as a bias adjustment transistor for adjusting bias in each of the transmission buffer circuit and the amplitude amplification buffer circuit, respectively, and bias adjustments are made simultaneously.

Abstract: LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.

Abstract: Each storage unit is provided with a table for storing a corresponding unit ID and count value. The controller receives a formatting instruction specifying a first unit ID, and updates the count value on a table corresponding to the first unit ID. The controller receives a write command specifying a second unit ID, acquires a count value corresponding to the second unit ID from the table, and attaches the count value to the data, and writes the data to the storage unit. When a read command specifying the second unit ID is received, the controller reads the data from the storage unit, acquires the count value corresponding to the second unit ID from the table, compares this count value and the count value attached to the read data, sends the read data to the transmission source of the command if these values match, and does not send the data to the transmission source of the command if these values do not match.

Abstract: A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when the signal transmission line is switched between the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched.

Abstract: To provide a storage system which enables usage of a greater volume of cache than that of a cache memory provided to a disk array control unit, including a first disk array control unit, a second disk array control unit, a plurality of disks, and a disk array control unit communication path between a first data transfer control unit and a second data transfer control unit, wherein the first data transfer control unit selectively sets either a first path through a first host input/output control unit, the first data transfer control unit, and a first disk input/output control unit, or a second path through the first host input/output control unit, the first data transfer control unit, the disk array control unit communication path, the second data transfer control unit, and a second disk input/output control unit, and then processes a data input/output request from a host.

Abstract: In order to manage the various types of attribute information within the storage-device system, the storage-device system includes the following databases within a file-access controlling memory: a database for managing index information for managing contents of the files, and an index retrieval program, a database for managing the attribute information on the files, and a database for managing storage positions of blocks configuring a file. When the storage-device system receives an access request to a file, the utilization of these databases allows the storage-device system to make the access to the access-target file.

Abstract: In order to manage the various types of attribute information within the storage-device system, the storage-device system includes the following databases within a file-access controlling memory: a database for managing index information for managing contents of the files, and an index retrieval program, a database for managing the attribute information on the files, and a database for managing storage positions of blocks configuring a file. When the storage-device system receives an access request to a file, the utilization of these databases allows the storage-device system to make the access to the access-target file.

Abstract: In a storage system that manages update prohibition (WORM) information, when time management is not performed with precision, there arises a possibility that an update prohibition (WORM) attribute may be erased before a preservation period expires.

Abstract: The fact that data stored in a storage system is not updated for a given period is proven to a third party. A method of managing data that is given an update prohibitive attribute includes a step of storing, in a management server, information on an end time of the update prohibitive attribute which is received from a storage system, a step of receiving, from the storage system, a request for permission to change the update prohibitive attribute given to the data and obtaining, from the management server, the end time of the update prohibitive attribute given to the data on which the request is made, a step of judging whether or not the end time of the update prohibitive attribute has passed, and a step of sending, when it is judged that the end time of the update prohibitive attribute given to the data on which the request is made has passed, permission to change the update prohibitive attribute given to the data on which the request is made to the storage system.

Abstract: A disk array controller 11 decides whether a command received from a host 20-22 is a write command or a read command. If it is a write command, the disk array controller 11 generates a data block, parity block and redundancy code block from the received data, and stores the data dispersed among the plurality of disk devices D00 -D0N. If it is a read command, the disk array controller 11 uses the parity block and redundancy code block to decide whether there is an error in the read data block, and in the event there is an error in the read data block, it is corrected using the parity block and redundancy code block.

Abstract: To provide a storage system which enables usage of a greater volume of cache than that of a cache memory provided to a disk array control unit, including a first disk array control unit, a second disk array control unit, a plurality of disks, and a disk array control unit communication path between a first data transfer control unit and a second data transfer control unit, wherein the first data transfer control unit selectively sets either a first path through a first host input/output control unit, the first data transfer control unit, and a first disk input/output control unit, or a second path through the first host input/output control unit, the first data transfer control unit, the disk array control unit communication path, the second data transfer control unit, and a second disk input/output control unit, and then processes a data input/output request from a host

Abstract: In order to manage the various types of attribute information within the storage-device system, the storage-device system includes the following databases within a file-access controlling memory: a database for managing index information for managing contents of the files, and an index retrieval program, a database for managing the attribute information on the files, and a database for managing storage positions of blocks configuring a file. When the storage-device system receives an access request to a file, the utilization of these databases allows the storage-device system to make the access to the access-target file.

Abstract: A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.

Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Abstract: A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.