Abstract: A memory system includes a controller that writes internal information concerning an operation state of the memory system in a special LBA area allocated to a predetermined logical address range in a second storing memory and writes the internal information in a first storing memory, and reads out, when the memory system is started up, the internal information to manage the operation state. The controller stores the internal information written in the first storing memory in the second storing memory as a snapshot when a predetermined condition is satisfied and, when an error occurs and the internal information written in the special LBA area cannot be read out when the memory system is started up, captures the internal information stored as the snapshot into the first storing memory and reads out the internal information.

Abstract: A memory system includes a controller that reads out, data written in a nonvolatile second storing area, from which data is read out and in which data is written in a page unit, to a first storing area as a cache memory included in a semiconductor memory and transfers the data to the host apparatus. The controller performs, when a readout request from the host apparatus satisfies a predetermined condition, at least one of first pre-fetch for reading out, to the first storing area data from a terminal end of a logical address range designated by a readout request being currently processed to a boundary of a logical address aligned in the page unit and a second pre-fetch for reading out data from the boundary of the logical address aligned in the page unit to a next boundary of the logical address.

Abstract: A data output buffer circuit for a semiconductor integrated circuit has a plurality of output buffer circuits. Each output buffer circuit has an input terminal for receiving input data and an output buffer having first and second switching circuits serially connected between two high and low power source terminals. Each of the first and second switching circuits has a control terminal for turning on and off each of the first and second switching circuits upon receipt of a control signal at the control terminals. A timing signal input terminal receives a timing signal with which the output buffer circuit operates in synchronism. A timing switch connects the next stage of the input terminal and is turned on by the timing signal. A delay signal is connected between the timing switch means and the control terminals of the first and second switching circuits and delays the input data from the input terminal and transmits the delayed input data to the control terminals of the first and second switching circuits.