Abstract: A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region adjacent to the gate structure. A top of the dielectric cap is oxidized. After oxidizing the top of the dielectric cap, an etch stop layer is deposited over the dielectric cap and an interlayer dielectric (ILD) layer over the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending though the ILD layer and the etch stop layer. A source/drain via is filled in the via opening.

Abstract: A method comprises forming a source/drain contact over a source/drain region; forming an etch stop layer over the source/drain contact and an interlayer dielectric (ILD) layer over the etch stop layer; performing a first etching process to form a via opening extending though the ILD layer and a recess in the etch stop layer; oxidizing a sidewall of the recess in the etch stop layer; after oxidizing the sidewall of the recess in the etch stop layer, performing a second etching process to extend the via opening down to the source/drain contact; and after performing the second etching process, forming a source/drain via in the via opening.

Abstract: A method comprises forming a gate dielectric cap over a gate structure; forming source/drain contacts over the semiconductor substrate, with the gate dielectric cap laterally between the source/drain contacts; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the etch-resistant layer and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the via opening such that one of the source/drain contacts is exposed, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and depositing a metal material to fill the deepened via opening.

Abstract: A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region after forming the dielectric cap. A top of the dielectric cap is doped to form a doped region in the dielectric cap. After doping the top of the dielectric cap, a etch stop layer and an interlayer dielectric (ILD) layer are deposited over the dielectric cap. A via opening is formed to extend though the ILD layer and the etch stop layer to expose the source/drain contact. A source/drain via is filled in the via opening.

Abstract: A method comprises forming a gate structure over a semiconductor substrate; etching back the gate structure; forming a gate dielectric cap over the etched back gate structure; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.

Abstract: A wafer carrier including a rotation axis, a center flat region, a wafer distributing region and a plurality of wafer accommodating grooves is provided. The rotation axis passes through a center of the center flat region and a surface of the center flat region is a flat surface. The wafer distributing region surrounds the center flat region. The plurality of wafer accommodating grooves are disposed in the wafer distributing region and arranged in a single virtual loop. A diameter of each of the wafer accommodating grooves is D, and a radius of the center flat region is larger than 0.5D. A wafer carrier and a metal organic chemical vapor deposition apparatus using any of the above two wafer carriers are further provided.

Abstract: A light-emitting semiconductor substrate, which is applied to a light-emitting semiconductor structure, includes a base and a plurality of particle groups. The base includes an upper surface. The particle groups are on the upper surface or inside the base dispersedly, and each of the particle groups includes Sn, Sn compounds or combinations thereof.

Abstract: A tray structure adapted to a deposition apparatus is provided. The tray structure includes a first tray and a second tray, wherein the first tray is disposed on the deposition apparatus for control of temperature and includes a first carrying portion and at least one heat-conducting structure. The first carrying portion is disposed on a top surface of the first tray. The at least one heat-conducting structure is disposed in a recess of the first carrying portion. The second tray is disposed on the first carrying portion and the at least one heat-conducting structure.

Abstract: Herein disclosed are a wafer, a wafer testing system, and a method thereof. Said wafer testing method comprises the following steps. First, an incident light is provided toward a wafer. And, a wafer surface image corresponded to the wafer is generated. Then, determining whether the wafer surface image has a plurality of first strips and a plurality of second strips, and the plurality of first strips and the plurality of second strips are symmetrical.

Abstract: A heating apparatus including a rotating stage, a plurality of wafer carriers, a plurality of first heaters, and at least one second heater is provided. The rotating stage includes a rotating axis. The plurality of wafer carriers is disposed on the rotating stage. The rotating stage drives the wafer carriers to rotate by taking the rotating axis as a center. The plurality of first heaters is disposed under a first heating region of the rotating stage. There is a first spacing between any two adjacent first heaters. The at least one second heater is disposed under a second heating region of the rotating stage. There is a spacing between the second heating region and the first heating region, and the spacing is not equal to the first spacing. A chemical vapor deposition (CVD) system using the heating apparatus is also provided.

Abstract: A heating apparatus including a rotating stage, a plurality of wafer carriers, a first heater, and a second heater is provided. The rotating stage includes a rotating axis. The plurality of wafer carriers is disposed on the rotating stage. The rotating stage drives the wafer carriers to rotate on the rotating axis. The first heater is disposed under the rotating stage. The first heater includes a first width in a radial direction of the rotating stage. The second heater is disposed under the rotating stage. The second heater and the first heater are separated from each other. The second heater includes a second width in the radial direction of the rotating stage, and the first width is not equal to the second width. A chemical vapor deposition (CVD) system using the heating apparatus is also provided.

Abstract: A light emitting device includes an epitaxial structure. The epitaxial structure includes a first type semiconductor layer, a second type semiconductor layer and a light emitting layer. The first type semiconductor layer includes a first semiconductor sublayer. The light emitting layer is disposed between the first type semiconductor layer and the second type semiconductor layer. The first semiconductor sublayer includes a heavily doped part and a lightly doped part which are doped by a first type dopant. A doping concentration of the first type dopant in the heavily doped part is equal to 1018 atoms/cm3 or between 1017 atoms/cm3 and 1018 atoms/cm3. A doping concentration of the first type dopant in the lightly doped part is less than or equal to 1017 atoms/cm3.

Abstract: A patterned substrate includes a main base and a plurality of patterned structures. The main base has at least one device-disposed region and a cutting region surrounding the device-disposed region. The patterned structures are integratedly formed with the main base, and only distributed in the cutting region of the main base. The patterned structures are separated from each other.

Abstract: A nitride semiconductor structure and a semiconductor light emitting device are revealed. The semiconductor light emitting device includes a substrate disposed with a first type doped semiconductor layer and a second type doped semiconductor layer. A light emitting layer is disposed between the first type doped semiconductor layer and the second type doped semiconductor layer. The second type doped semiconductor layer is doped with a second type dopant at a concentration larger than 5×1019 cm ?3 while a thickness of the second type doped semiconductor layer is smaller than 30 nm. Thereby the semiconductor light emitting device provides a better light emitting efficiency.

Abstract: A wafer carrier including a rotation axis, a center flat region, a wafer distributing region, and a plurality of wafer accommodating grooves is provided. The rotation axis passes through the center of the center flat region. The wafer distributing region surrounds the center flat region. The plurality of wafer accommodating grooves are disposed in the wafer distributing region. The diameter of each of the wafer accommodation grooves is D, and the radius of the center flat region is 0.5D to 3D. A surface of the center flat region is a flat surface. A wafer carrier and a metal organic chemical vapor deposition apparatus using any of the above two wafer carriers are further provided.

Abstract: A light-emitting diode chip including a p-type semiconductor layer, a light-emitting layer, an n-type semiconductor layer, and a first metal electrode is provided. The light-emitting layer is disposed between the p-type semiconductor layer and the n-type semiconductor layer. The n-type semiconductor layer includes a first n-type semiconductor sub-layer, a second n-type semiconductor sub-layer, and an ohmic contact layer. The ohmic contact layer is disposed between the first n-type semiconductor sub-layer and the second n-type semiconductor sub-layer. The first metal electrode is disposed on the first n-type semiconductor sub-layer. A region of the first n-type semiconductor sub-layer located between the first metal electrode and the ohmic contact layer contains metal atoms diffusing from the first metal electrode, so as to form ohmic contact between the first metal electrode and the ohmic contact layer.

Abstract: A semiconductor structure includes a first-type doped semiconductor layer, a light emitting layer, a second-type doped semiconductor layer comprising AlxInyGa1-x-yN layers, at least one GaN based layer, and an ohmic contact layer. The light emitting layer is disposed on the first-type doped semiconductor layer, and the second-type doped semiconductor layer is disposed on the light emitting layer. The AlxInyGa1-x-yN layers stacked on the light emitting layer, where 0<x<1, 0?y<1, and 0<x+y<1, and the GaN based layer interposed between two of the AlxInyGa1-x-yN layers, and the ohmic contact layer is disposed on the AlxInyGa1-x-yN layers.

Abstract: A light emitting device includes an epitaxial structure. The epitaxial structure includes a first type semiconductor layer, a second type semiconductor layer and a light emitting layer. The first type semiconductor layer includes a first semiconductor sublayer. The light emitting layer is disposed between the first type semiconductor layer and the second type semiconductor layer. The first semiconductor sublayer includes a heavily doped part and a lightly doped part which are doped by a first type dopant. A doping concentration of the first type dopant in the heavily doped part is equal to 1018 atoms/cm3 or between 1017 atoms/cm3 and 1018 atoms/cm3. A doping concentration of the first type dopant in the lightly doped part is less than or equal to 1017 atoms/cm3.

Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from AlxGa1-xN (0<x<1) while the stress control layer is made from AlxInyGa1-x-yN (0<x<1, 0<y<1, 0<x+y<1). The light emitting layer has a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. There is one well layer disposed between the two barrier layers. Thereby the stress control layer not only improves crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer and the light emitting layer but also reduces effects of compressive stress on the well layer caused by material differences.

Abstract: A light-emitting diode chip including a p-type semiconductor layer, a light-emitting layer and an n-type semiconductor layer is provided. The light-emitting layer is disposed between the p-type semiconductor layer and the n-type semiconductor layer. A ratio of a sum of thicknesses of all semiconductor layers of the light-emitting diode chip over a maximum width of the light-emitting diode chip ranges from 0.02 to 1.5. A ratio of a sum of thicknesses of all semiconductor layers located in a side of the light-emitting layer toward the p-type semiconductor layer over the sum of thicknesses of all semiconductor layers of the light-emitting diode chip ranges from 0.05 to 0.2.