Patents by Inventor K. Paul Muller
K. Paul Muller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11235224Abstract: A method, system, and computer program product algorithmically analyzes scoring data from a competitive event where the scoring, determined by a plurality of evaluators, is based on subjective criteria. The method receives, and/or determines a scale factor associated with each evaluator. The method adjusts scores awarded by each evaluator, based on respectively corresponding scale factors, to arrive at normalized scores. The method, thereby minimizes influences of biases associated with the evaluators.Type: GrantFiled: November 30, 2020Date of Patent: February 1, 2022Assignee: International Business Machines CorporationInventors: Natesan Venkateswaran, Jayapreetha Natesan, K. Paul Muller, Brian Robert Prasky, Chunming Lin
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Patent number: 11169841Abstract: Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.Type: GrantFiled: March 17, 2020Date of Patent: November 9, 2021Assignee: Internationl Business Machines CorporationInventors: K Paul Muller, William V. Huott, Eberhard Engler, Christopher Raymond Conklin, Stephanie Lehrer, Andrew A. Turner
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Patent number: 11150971Abstract: Pattern recognition is used to proactively treat defects of repeating circuit topologies. A component of a computing environment is monitored for failures. The component includes one or more repeating circuit topologies. A determination is made as to whether a new failure within a repeating circuit topology of the one or more repeating circuit topologies has occurred within a predefined amount of time from a previous failure matching a selected pattern, in which the selected pattern indicates a non-contiguous growing defect. Based on determining the new failure has occurred within the predefined amount of time from the previous failure matching the selected pattern, corrective action for the component is proactively taken.Type: GrantFiled: April 7, 2020Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uma Srinivasan, K. Paul Muller, Kevin W. Kark, Pamela Antal
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Publication number: 20210311814Abstract: Pattern recognition is used to proactively treat defects of repeating circuit topologies. A component of a computing environment is monitored for failures. The component includes one or more repeating circuit topologies. A determination is made as to whether a new failure within a repeating circuit topology of the one or more repeating circuit topologies has occurred within a predefined amount of time from a previous failure matching a selected pattern, in which the selected pattern indicates a non-contiguous growing defect. Based on determining the new failure has occurred within the predefined amount of time from the previous failure matching the selected pattern, corrective action for the component is proactively taken.Type: ApplicationFiled: April 7, 2020Publication date: October 7, 2021Inventors: Uma Srinivasan, K. Paul Muller, Kevin W. Kark, Pamela Antal
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Publication number: 20210294640Abstract: Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.Type: ApplicationFiled: March 17, 2020Publication date: September 23, 2021Inventors: K Paul Muller, William V. Huott, Eberhard Engler, Christopher Raymond Conklin, Stephanie Lehrer, Andrew A. Turner
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Patent number: 10114649Abstract: An instruction control interface is provided for automatically controlling assigning of one or more instructions for processing by one or more processor cores of a computing device. The control interface separately monitors temperatures of multiple logic units within each processor core of the processor core(s) of the computing device, and controls assigning of one or more instructions for processing by a particular processor core(s) based, at least in part, on the separately monitored temperatures of the multiple logic units within the processor core(s).Type: GrantFiled: May 26, 2015Date of Patent: October 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: K. Paul Muller, David S. Wolpert
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Patent number: 10084598Abstract: Technical solutions are described for authenticating a hosting system prior to securely deploying a shrouded virtual server. An example method includes receiving, by a hypervisor, a request for a public certificate, from a client device that requested the virtual server, and sending the public certificate of the hosting system that executes the hypervisor. The method also includes receiving, in response to the public certificate being successfully authenticated by the client device using a third-party verification system, a session key based on a public key included in the public certificate. The method also includes decrypting the session key using a private key, where the private key is pre-installed in the hosting system by a manufacturer of the hosting system, and sending an acknowledgement message encrypted using the session key. The method also includes establishing a secure communication between the client device and the hypervisor using the session key.Type: GrantFiled: December 27, 2017Date of Patent: September 25, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Khary J. Alexander, Reinhard T. Buendgen, K. Paul Muller, James A. O'Connor, William J. Rooney, Tiberiu Suto, Craig R. Walters, Sean Swehla
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Patent number: 9998459Abstract: Technical solutions are described for securely deploying a shrouded virtual server. An example method includes sending, by a host manager, authentication information of a hosting system to a client device in response to a request from the client device. The \method also includes receiving a request to deploy a virtual server using a shrouded mode. The method also includes deploying a preconfigured hypervisor on the hosting system, where the preconfigured hypervisor is deployed in an immutable mode that disables changes to security settings of the preconfigured hypervisor. The method also includes deploying, by the preconfigured hypervisor, a preconfigured boot image as an instance of the virtual server on the preconfigured hypervisor. The method also includes sending, by the host manager, an identifier of the virtual server for receipt by the client device.Type: GrantFiled: November 17, 2017Date of Patent: June 12, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Khary J. Alexander, Utz Bacher, Reinhard T. Buendgen, Patrick J. Callaghan, John C. Dayka, Thomas B. Mathias, K. Paul Muller, James A. O'Connor, William J. Rooney, Kurt N. Schroeder, Peter G. Spera, Tiberiu Suto, Sean Swehla, Stefan Usenbinz, Craig R. Walters
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Publication number: 20180102899Abstract: Technical solutions are described for authenticating a hosting system prior to securely deploying a shrouded virtual server. An example method includes receiving, by a hypervisor, a request for a public certificate, from a client device that requested the virtual server, and sending the public certificate of the hosting system that executes the hypervisor. The method also includes receiving, in response to the public certificate being successfully authenticated by the client device using a third-party verification system, a session key based on a public key included in the public certificate. The method also includes decrypting the session key using a private key, where the private key is pre-installed in the hosting system by a manufacturer of the hosting system, and sending an acknowledgement message encrypted using the session key. The method also includes establishing a secure communication between the client device and the hypervisor using the session key.Type: ApplicationFiled: December 27, 2017Publication date: April 12, 2018Inventors: Khary J. Alexander, Reinhard T. Buendgen, K. Paul Muller, James A. O'Connor, William J. Rooney, Tiberiu Suto, Craig R. Walters
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Patent number: 9912478Abstract: Technical solutions are described for authenticating a hosting system prior to securely deploying a shrouded virtual server. An example method includes receiving, by a hypervisor, a request for a public certificate, from a client device that requested the virtual server, and sending the public certificate of the hosting system that executes the hypervisor. The method also includes receiving, in response to the public certificate being successfully authenticated by the client device using a third-party verification system, a session key based on a public key included in the public certificate. The method also includes decrypting the session key using a private key, where the private key is pre-installed in the hosting system by a manufacturer of the hosting system, and sending an acknowledgement message encrypted using the session key. The method also includes establishing a secure communication between the client device and the hypervisor using the session key.Type: GrantFiled: December 14, 2015Date of Patent: March 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Khary J. Alexander, Reinhard T. Buendgen, K. Paul Muller, James A. O'Connor, William J. Rooney, Tiberiu Suto, Craig R. Walters
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Publication number: 20180063136Abstract: Technical solutions are described for securely deploying a shrouded virtual server. An example method includes sending, by a host manager, authentication information of a hosting system to a client device in response to a request from the client device. The \method also includes receiving a request to deploy a virtual server using a shrouded mode. The method also includes deploying a preconfigured hypervisor on the hosting system, where the preconfigured hypervisor is deployed in an immutable mode that disables changes to security settings of the preconfigured hypervisor. The method also includes deploying, by the preconfigured hypervisor, a preconfigured boot image as an instance of the virtual server on the preconfigured hypervisor. The method also includes sending, by the host manager, an identifier of the virtual server for receipt by the client device.Type: ApplicationFiled: November 17, 2017Publication date: March 1, 2018Inventors: Khary J. Alexander, Utz Bacher, Reinhard T. Buendgen, Patrick J. Callaghan, John C. Dayka, Thomas B. Mathias, K. Paul Muller, James A. O'Connor, William J. Rooney, Kurt N. Schroeder, Peter G. Spera, Tiberiu Suto, Sean Swehla, Stefan Usenbinz, Craig R. Walters
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Patent number: 9882901Abstract: Technical solutions are described for securely deploying a shrouded virtual server. An example method includes sending, by a host manager, authentication information of a hosting system to a client device in response to a request from the client device. The \method also includes receiving a request to deploy a virtual server using a shrouded mode. The method also includes deploying a preconfigured hypervisor on the hosting system, where the preconfigured hypervisor is deployed in an immutable mode that disables changes to security settings of the preconfigured hypervisor. The method also includes deploying, by the preconfigured hypervisor, a preconfigured boot image as an instance of the virtual server on the preconfigured hypervisor. The method also includes sending, by the host manager, an identifier of the virtual server for receipt by the client device.Type: GrantFiled: December 14, 2015Date of Patent: January 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Khary J. Alexander, Utz Bacher, Reinhard T. Buendgen, Patrick J. Callaghan, John C. Dayka, Thomas B. Mathias, K. Paul Muller, James A. O'Connor, William J. Rooney, Kurt N. Schroeder, Peter G. Spera, Tiberiu Suto, Sean Swehla, Stefan Usenbinz, Craig R. Walters
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Publication number: 20170171164Abstract: Technical solutions are described for authenticating a hosting system prior to securely deploying a shrouded virtual server. An example method includes receiving, by a hypervisor, a request for a public certificate, from a client device that requested the virtual server, and sending the public certificate of the hosting system that executes the hypervisor. The method also includes receiving, in response to the public certificate being successfully authenticated by the client device using a third-party verification system, a session key based on a public key included in the public certificate. The method also includes decrypting the session key using a private key, where the private key is pre-installed in the hosting system by a manufacturer of the hosting system, and sending an acknowledgement message encrypted using the session key. The method also includes establishing a secure communication between the client device and the hypervisor using the session key.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: Khary J. Alexander, Reinhard T. Buendgen, K. Paul Muller, James A. O'Connor, William J. Rooney, Tiberiu Suto, Craig R. Walters
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Publication number: 20170171197Abstract: Technical solutions are described for securely deploying a shrouded virtual server. An example method includes sending, by a host manager, authentication information of a hosting system to a client device in response to a request from the client device. The \method also includes receiving a request to deploy a virtual server using a shrouded mode. The method also includes deploying a preconfigured hypervisor on the hosting system, where the preconfigured hypervisor is deployed in an immutable mode that disables changes to security settings of the preconfigured hypervisor. The method also includes deploying, by the preconfigured hypervisor, a preconfigured boot image as an instance of the virtual server on the preconfigured hypervisor. The method also includes sending, by the host manager, an identifier of the virtual server for receipt by the client device.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: Khary J. Alexander, Utz Bacher, Reinhard T. Buendgen, Patrick J. Callaghan, John C. Dayka, Thomas B. Mathias, K. Paul Muller, James A. O'Connor, William J. Rooney, Kurt N. Schroeder, Peter G. Spera, Tiberiu Suto, Sean Swehla, Stefan Usenbinz, Craig R. Walters
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Patent number: 9626220Abstract: A multiple processor core computer system interface assigns instructions to partially functional processor cores based on processing resources available in each partially functional core. Each processor core is labeled as fully functional, partially functional, or non-functional, and an indicator is provided for each partially functional processor core that shows what processing resources are available for a respective core. The indicators can be stored in memory after final test. The interface can monitor cores for changes in available resources and update respective indicators, such as by superseding an existing indicator with or creating a new indicator in read-write memory.Type: GrantFiled: January 13, 2015Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: Marcel Mitran, K. Paul Muller, William J. Rooney, Joran S. C. Siu, David S. Wolpert
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Patent number: 9569582Abstract: A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.Type: GrantFiled: January 3, 2014Date of Patent: February 14, 2017Assignee: International Business Machines CorporationInventors: Eli Arbel, Pradip Bose, Prabhakar Kudva, Shiri Moran, K. Paul Muller
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Publication number: 20160350117Abstract: An instruction control interface is provided for automatically controlling assigning of one or more instructions for processing by one or more processor cores of a computing device. The control interface separately monitors temperatures of multiple logic units within each processor core of the processor core(s) of the computing device, and controls assigning of one or more instructions for processing by a particular processor core(s) based, at least in part, on the separately monitored temperatures of the multiple logic units within the processor core(s).Type: ApplicationFiled: May 26, 2015Publication date: December 1, 2016Inventors: K. Paul MULLER, David S. WOLPERT
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Publication number: 20160203023Abstract: A multiple processor core computer system interface assigns instructions to partially functional processor cores based on processing resources available in each partially functional core. Each processor core is labeled as fully functional, partially functional, or non-functional, and an indicator is provided for each partially functional processor core that shows what processing resources are available for a respective core. The indicators can be stored in memory after final test. The interface can monitor cores for changes in available resources and update respective indicators, such as by superseding an existing indicator with or creating a new indicator in read-write memory.Type: ApplicationFiled: January 13, 2015Publication date: July 14, 2016Inventors: Marcel Mitran, K. Paul Muller, William J. Rooney, Joran S.C. Siu, David S. Wolpert
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Publication number: 20160154921Abstract: A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.Type: ApplicationFiled: January 3, 2014Publication date: June 2, 2016Applicant: International Business Machines CorporationInventors: Eli Arbel, Pradip Bose, Prabhakar Kudva, Shiri Moran, K. Paul Muller
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Patent number: 9355746Abstract: Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.Type: GrantFiled: September 30, 2014Date of Patent: May 31, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luiz C. Alves, William J. Clarke, Christopher R. Conklin, William V. Huott, Kevin W. Kark, Thomas J. Knips, K. Paul Muller