Patents by Inventor K. Paul Muller
K. Paul Muller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090134925Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: ApplicationFiled: September 19, 2007Publication date: May 28, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Patent number: 7491598Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.Type: GrantFiled: December 14, 2007Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Christopher D. Sheraw, Alyssa C. Bonnoit, K. Paul Muller, Werner Rausch
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Publication number: 20080303070Abstract: Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.Type: ApplicationFiled: August 13, 2008Publication date: December 11, 2008Inventors: Paul D. Agnello, Rajeev Malik, K. Paul Muller
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Patent number: 7459384Abstract: Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.Type: GrantFiled: June 28, 2004Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Paul D. Agnello, Rajeev Malik, K. Paul Muller
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Patent number: 7361959Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.Type: GrantFiled: November 28, 2005Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: Christopher D. Sheraw, Alyssa C. Bonnoit, K. Paul Muller, Werner Rausch
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Patent number: 7304352Abstract: A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.Type: GrantFiled: April 21, 2005Date of Patent: December 4, 2007Assignee: International Business Machines CorporationInventors: K. Paul Muller, Kevin A. Batson, Michael J. Lee
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Patent number: 7288445Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and ?0.5V for pFETs.Type: GrantFiled: May 9, 2005Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Andres Bryant, Meikei Ieong, K. Paul Muller, Edward J. Nowak, David M. Fried, Jed Rankin
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Publication number: 20070106968Abstract: An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.Type: ApplicationFiled: November 8, 2005Publication date: May 10, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Culp, Lars Liebmann, Rajeev Malik, K. Paul Muller, Shreesh Narasimha, Stephen Runyon, Patrick Williams
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Patent number: 7087477Abstract: The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.Type: GrantFiled: November 12, 2004Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventors: David M. Fried, Randy W. Mann, K. Paul Muller, Edward J. Nowak
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Patent number: 6967351Abstract: The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.Type: GrantFiled: December 4, 2001Date of Patent: November 22, 2005Assignee: International Business Machines CorporationInventors: David M. Fried, Randy W. Mann, K. Paul Muller, Edward J. Nowak
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Patent number: 6960806Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and ?0.5V for pFETs.Type: GrantFiled: June 21, 2001Date of Patent: November 1, 2005Assignee: International Business Machines CorporationInventors: Andres Bryant, Meikei Ieong, K. Paul Muller, Edward J. Nowak, David M. Fried, Jed Rankin
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Patent number: 6913960Abstract: The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-source/drain capacitance. The low body-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.Type: GrantFiled: May 11, 2004Date of Patent: July 5, 2005Assignee: International Business Machines CorporationInventors: Andres Bryant, K. Paul Muller, Edward J. Nowak
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Publication number: 20040207019Abstract: The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-source/drain capacitance. The low body-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.Type: ApplicationFiled: May 11, 2004Publication date: October 21, 2004Inventors: Andres Bryant, K. Paul Muller, Edward J. Nowak
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Patent number: 6774437Abstract: The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-to-source/drain capacitance. The low body-to-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.Type: GrantFiled: January 7, 2002Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventors: Andres Bryant, K. Paul Muller, Edward J. Nowak
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Patent number: 6657261Abstract: A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region as well as a method of fabricating the same are provided.Type: GrantFiled: January 9, 2001Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Fariborz Assaderaghi, Tze-chiang Chen, K. Paul Muller, Edward J. Nowak, Devendra K. Sadana, Ghavam G. Shahidi
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Patent number: 6645795Abstract: Steep concentration gradients are achieved in semiconductor device of small sizes formed on SOI or double SOI wafers by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects. In the case of SOI wafers greater uniformity of electrical characteristics are achieved using the high quality of semiconductor material made available therein consistent with the relatively thin active layer.Type: GrantFiled: May 3, 2001Date of Patent: November 11, 2003Assignee: International Business Machines CorporationInventors: K. Paul Muller, Dominic J. Schepis, Ghavam G. Shahidi
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Publication number: 20030127690Abstract: The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-to-source/drain capacitance. The low body-to-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.Type: ApplicationFiled: January 7, 2002Publication date: July 10, 2003Inventors: Andres Bryant, K. Paul Muller, Edward J. Nowak
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Publication number: 20030102518Abstract: The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}.Type: ApplicationFiled: December 4, 2001Publication date: June 5, 2003Applicant: International Business Machines CorporationInventors: David M. Fried, Randy W. Mann, K. Paul Muller, Edward J. Nowak
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Patent number: 6541317Abstract: Steep concentration gradients are achieved in semiconductor device of small sizes by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects.Type: GrantFiled: May 3, 2001Date of Patent: April 1, 2003Assignee: International Business Machines CorporationInventors: K. Paul Muller, Dominic J. Schepis, Ghavam G. Shahidi
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Patent number: 6537418Abstract: A gas distribution plate (60) for a semiconductor processing chamber (86) includes a gas distribution plate for distributing gases across a surface of a semiconductor wafer (84) to be processed in the chamber. The gas distribution plates has a substantially planar member having gas outlets for distributing a reactant gas across the surface of the semiconductor wafer, the gas outlet means includes a plurality of apertures (66) defined in said planar member, the plurality of apertures having different areas at predetermined locations to adjust etching gas flow. A pump (80) is provided for evacuating a reactant-product gas created across the surface of the semiconductor wafer during wafer processing.Type: GrantFiled: September 19, 1997Date of Patent: March 25, 2003Assignee: Siemens AktiengesellschaftInventors: K. Paul Muller, Bertrand Flietner, Klaus Roithner