Abstract: A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.

Abstract: Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.

Abstract: A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

Abstract: Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.

Abstract: Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.

Abstract: Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.

Abstract: A modular refrigeration unit (MRU) health monitor includes a log data input configured to receive log data from an MRU, the log data comprising a plurality of datapoints, each of the plurality of datapoints comprising a position of a control valve of the MRU and a corresponding time; and MRU health monitoring logic configured to determine a plurality of MRU parameters from log data received on the log data input; determine a plurality of MRU health flags based on the MRU parameters; add the plurality of MRU health flags to determine an MRU health score; determine whether the MRU health score is higher than a replacement threshold; and indicate replacement of the MRU in the event the MRU health score is higher than the replacement threshold.

Abstract: A method for modular refrigeration unit (MRU) health monitoring includes receiving log data on a log data input from the MRU by a MRU health monitor, the log data comprising a plurality of datapoints, each of the plurality of datapoints comprising a position of a control valve of the MRU and a corresponding time; determining by the MRU health monitor a plurality of MRU parameters from the log data; determining a plurality of MRU health flags based on the MRU parameters; adding the plurality of MRU health flags to determine an MRU health score; determining whether the MRU health score is higher than a replacement threshold; and indicating replacement of the MRU in the event the MRU health score is higher than the replacement threshold.

Abstract: A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.

Abstract: A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

Abstract: A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction. The method further includes adding a product code to the array, the product code including applying the second error control mechanism to a plurality of bits of the first error control mechanism.

Abstract: Automated control of a cooling system cooling at least one electronic component is provided. The control includes monitoring over a period of time variation of an operational variable of the cooling system or of the at least one electronic component, and based, at least in part, on variation of the operational variable over the period of time, automatically determining whether to adjust control of the cooling system to limit variation of the operational variable. In one implementation, depending on the variation of the operational variable, and whether control of the cooling system has been previously adjusted, the method may further include automatically determining a probability of fail or an expected residual life of the cooling system, and responsive to the predicted probability of fail exceeding a first acceptable threshold or the expected residual life being below a second acceptable threshold, automatically scheduling for a cooling system repair or replacement.

Abstract: A method of remotely monitoring electromigration in an electronic chip includes sensing, at a first location, at least one temperature value of the electronic chip, sending the at least one temperature value to a remote monitoring system, accumulating a plurality of temperature values of the electronic chip at the monitoring system during a reporting period, calculating an Electromigration Life Consumed (EMLC) value of the electronic chip for the reporting period based on the plurality of temperature values, determining whether the EMLC of the electronic chip is above a predetermined threshold, and providing a signal when the EMLC of the electronic chip is above the predetermined threshold.

Abstract: Automated control of a cooling system cooling at least one electronic component is provided. The control includes monitoring over a period of time variation of an operational variable of the cooling system or of the at least one electronic component, and based, at least in part, on variation of the operational variable over the period of time, automatically determining whether to adjust control of the cooling system to limit variation of the operational variable. In one implementation, depending on the variation of the operational variable, and whether control of the cooling system has been previously adjusted, the method may further include automatically determining a probability of fail or an expected residual life of the cooling system, and responsive to the predicted probability of fail exceeding a first acceptable threshold or the expected residual life being below a second acceptable threshold, automatically scheduling for a cooling system repair or replacement.

Abstract: A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.

Abstract: A method of remotely monitoring electromigration in an electronic chip includes sensing, at a first location, at least one temperature value of the electronic chip, sending the at least one temperature value to a remote monitoring system, accumulating a plurality of temperature values of the electronic chip at the monitoring system during a reporting period, calculating an Electromigration Life Consumed (EMLC) value of the electronic chip for the reporting period based on the plurality of temperature values, determining whether the EMLC of the electronic chip is above a predetermined threshold, and providing a signal when the EMLC of the electronic chip is above the predetermined threshold.

Abstract: A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.

Abstract: A method for providing error detection, or error detection combined with error correction, to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding an error control mechanism to the array of storage cells in the insensitive direction. The insensitive direction is a direction perpendicular to a width of a gate conductor of the storage cells.

Abstract: A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction. The method further includes adding a product code to the array, the product code including applying the second error control mechanism to a plurality of bits of the first error control mechanism.

Abstract: A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.