Abstract: A method for identifying a nucleic acid template that include (a) providing a plurality of primer-template hybrids, wherein a first hybrid of the plurality includes a first template hybridized to a first primer, and wherein a second hybrid of the plurality includes a second template hybridized to a second primer, the second primer having a ternary complex inhibitor moiety at the 3? end; (b) delivering polymerases and nucleotides to the plurality, whereby the first hybrid binds a polymerase and nucleotide to form a stabilized ternary complex and whereby the second hybrid does not bind a polymerase and nucleotide to form a stabilized ternary complex; and (c) detecting the stabilized ternary complex to identify the first template.

Abstract: A multi-level photovoltaic cell comprises a substrate layer and a plurality of photovoltaic cells positioned above the substrate layer. Each photovoltaic cell has a top contact layer and a bottom contact layer connected in series such that the top contact layer of the first photovoltaic cell is connected to the bottom contact layer of a next photovoltaic cell until the last photovoltaic cell is connected. A different voltage is output between the substrate layer and the top contact layer of each photovoltaic cell. Another multi-level photovoltaic cell comprises a substrate layer and a plurality of photovoltaic cells stacked vertically above the substrate layer. Each photovoltaic cell comprises an active layer separated from the next photovoltaic cell by an etch stop layer until a last photovoltaic cell is reached. A different voltage is output between the substrate layer and the active layer of each photovoltaic cell.

Abstract: Compositions and methods are provided for the inhibition of the function of RNA guided endonucleases, including the identification and use of such inhibitors.

Abstract: A method for determining sequences from sense and antisense strands of a nucleic acid, including (a) providing a nucleic acid cluster attached to a solid support, wherein the nucleic acid cluster includes a sense strand and an antisense strand of a concatemer, the concatemer including multiple copies of a sequence unit, the sequence unit including a target sequence and a primer binding site; (b) hybridizing a primer to a primer binding site in the antisense strand; (c) extending the primer along the antisense strand to determine the sequence from at least a portion of the target sequence in the antisense strand; (d) hybridizing a second primer to a primer binding site in the sense strand; and (e) extending the second primer along the sense strand to determine the sequence from at least a portion of the target sequence in the sense strand.

Abstract: A method for identifying a nucleic acid template that includes (a) providing a plurality of primer-template hybrids, wherein a first hybrid of the plurality includes a first template hybridized to a first primer, and wherein a second hybrid of the plurality includes a second template hybridized to a second primer, the second primer having a ternary complex inhibitor moiety at the 3? end; (b) delivering polymerases and nucleotides to the plurality, whereby the first hybrid binds a polymerase and nucleotide to form a stabilized ternary complex and whereby the second hybrid does not bind a polymerase and nucleotide to form a stabilized ternary complex; and (c) detecting the stabilized ternary complex to identify the first template.

Abstract: A true random number generator includes a latch circuit, a noise circuit coupled to the latch circuit and an equalization circuit coupled to the inputs of the latch circuit, the equalization circuit being configured to maintain the latch circuit in a balanced state and to allow the latch circuit to resolve from a metastable state based on a timing control. A method of generating a random number output includes maintaining a latch circuit in a balanced state by turning on an equalization circuit coupled to the inputs of the latch circuit, coupling at least one noise source to the latch circuit, allowing the latch circuit to resolve from a metastable state by turning off the equalization circuit and repeatedly turning the equalization circuit on and off based on a timing control.

Abstract: A Bharatnatyam headgear comprising a wearable hair net, the hair net being pliable and expandable to be worn over a dancer's head and covering the head, the wearable hair net matching a color of the dancer's hair. A circular piece is affixed to the hair net. The circular piece is capable of being positioned in a middle of a forehead at a forward end of the hair partition of the dancer. A forehead piece is affixed to the hair net, the forehead piece extending in a horizontal direction capable of being positioned to coincide with a hairline in a left and right direction and extending at least beyond eyebrows of the dancer. A vertical piece is affixed to the hair net, the vertical piece being attached to the circular piece and extending across a middle of the head to cover the hair partition.

Abstract: A Bharatnatyam headgear comprising a wearable hair net, the hair net being pliable and expandable to be worn over a dancer's head and covering the head, the wearable hair net matching a color of the dancer's hair. A circular piece is affixed to the hair net. The circular piece is capable of being positioned in a middle of a forehead at a forward end of the hair partition of the dancer. A forehead piece is affixed to the hair net, the forehead piece extending in a horizontal direction capable of being positioned to coincide with a hairline in a left and right direction and extending at least beyond eyebrows of the dancer. A vertical piece is affixed to the hair net, the vertical piece being attached to the circular piece and extending across a middle of the head to cover the hair partition.

Abstract: A true random number generator includes a latch circuit, a noise circuit coupled to the latch circuit and an equalization circuit coupled to the inputs of the latch circuit, the equalization circuit being configured to maintain the latch circuit in a balanced state and to allow the latch circuit to resolve from a metastable state based on a timing control. A method of generating a random number output includes maintaining a latch circuit in a balanced state by turning on an equalization circuit coupled to the inputs of the latch circuit, coupling at least one noise source to the latch circuit, allowing the latch circuit to resolve from a metastable state by turning off the equalization circuit and repeatedly turning the equalization circuit on and off based on a timing control.

Abstract: A Bharatnatyam headgear comprising a wearable hair net, the hair net being pliable and expandable to be worn over a dancer's head and covering the head, the wearable hair net matching a color of the dancer's hair. A circular piece is affixed to the hair net. The circular piece is capable of being positioned in a middle of a forehead at a forward end of the hair partition of the dancer. A forehead piece is affixed to the hair net, the forehead piece extending in a horizontal direction capable of being positioned to coincide with a hairline in a left and right direction and extending at least beyond eyebrows of the dancer. A vertical piece is affixed to the hair net, the vertical piece being attached to the circular piece and extending across a middle of the head to cover the hair partition.

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Abstract: A multi-level photovoltaic cell comprises a substrate layer and a plurality of photovoltaic cells positioned above the substrate layer. Each photovoltaic cell has a top contact layer and a bottom contact layer connected in series such that the top contact layer of the first photovoltaic cell is connected to the bottom contact layer of a next photovoltaic cell until the last photovoltaic cell is connected. A different voltage is output between the substrate layer and the top contact layer of each photovoltaic cell. Another multi-level photovoltaic cell comprises a substrate layer and a plurality of photovoltaic cells stacked vertically above the substrate layer. Each photovoltaic cell comprises an active layer separated from the next photovoltaic cell by an etch stop layer until a last photovoltaic cell is reached. A different voltage is output between the substrate layer and the active layer of each photovoltaic cell.

Abstract: Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.

Abstract: Technologies are generally described for the display of images by employing monotonic matrix factorization and sub-frame approximation image integration. In some examples, drive signals for a display device may be generated by iteratively applying a monotonic non-negative matrix factorization (NNMF) process to source image data. A given iteration of the monotonic NNMF process may result in approximation image data, partial sum image data, and residue image data, some or all of which may be further processed via subsequent iterations of the monotonic NNMF process. A generated approximation image data may then be displayed during a sub-frame time interval by selective activation of multiple row and column drivers. A series of such displayed approximation image data may effectively correspond to the original source image. In particular, the monotonic NNMF process may allow the generation of non-negative residue image data without the use of element reduction.

Abstract: In some examples, a memory device may be configured to use shared read circuitry to sample a voltage drop across both a bit cell and a resistive circuit in order to perform a comparison that produces an output corresponding to the bit stored in the bit cell. The shared read circuitry can include a shared sense amplifier as well as shared N-MOS and P-MOS followers used to apply read voltages across the bit cell and resistive circuit.

Abstract: In some examples, a memory device may be configured to use shared read circuitry to sample a voltage drop across both a bit cell and a resistive circuit in order to perform a comparison that produces an output corresponding to the bit stored in the bit cell. The shared read circuitry can include a shared sense amplifier as well as shared N-MOS and P-MOS followers used to apply read voltages across the bit cell and resistive circuit.

Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined.

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

Abstract: In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.