Abstract: In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.

Abstract: In some examples, a memory device may be configured to utilize differential bit cells formed from two or more tunnel junctions. In some cases, the tunnel junctions forming the differential bit cell may be arranged to utilize shared read circuitry to reduce device mismatch. For instance, the read operations associated with both tunnel junction may be time multiplexed such that the same preamplifier circuitry may sense voltages representative of the tunnel junctions.

Abstract: In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.

Abstract: Technologies are generally described for the display of images by employing monotonic matrix factorization and sub-frame approximation image integration. In some examples, drive signals for a display device may be generated by iteratively applying a monotonic non-negative matrix factorization (NNMF) process to source image data. A given iteration of the monotonic NNMF process may result in approximation image data, partial sum image data, and residue image data, some or all of which may be further processed via subsequent iterations of the monotonic NNMF process. A generated approximation image data may then be displayed during a sub-frame time interval by selective activation of multiple row and column drivers. A series of such displayed approximation image data may effectively correspond to the original source image. In particular, the monotonic NNMF process may allow the generation of non-negative residue image data without the use of element reduction.

Abstract: Drive signals for a display device may be generated using Separable Non-negative Matrix Series Representation (SNMSR) of source image data and applying a nonnegative matrix factorization (NNMF) process to source image data to generate approximation image data (Ii), partial sum image data (Pi) and residue image data (Ji). Iteratively, NNMF may be applied to Ji such that subsequent Ii and Ji may be generated, where each Ii can be associated with a corresponding sub-frame image. At each iteration, the Ii may be sent to the display buffer for selective activation of multiple row and column drivers during a single sub-frame interval. At each iteration, a determination may be made if a predetermined criterion is satisfied. The iterations may be terminated and the series truncated when the predetermined criterion is satisfied. Integration of the sub-frame images displayed over a complete frame interval by human eye effectively corresponds to the source image.

Abstract: In some examples, a memory device may be configured to utilize differential bit cells formed from two or more tunnel junctions. In some cases, the tunnel junctions forming the differential bit cell may be arranged to utilize shared read circuitry to reduce device mismatch. For instance, the read operations associated with both tunnel junction may be time multiplexed such that the same preamplifier circuitry may sense voltages representative of the tunnel junctions.

Abstract: In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.

Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined.

Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined.

Abstract: Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current comparison at a second bias state between a mock bit line and a bit line is used to determine the state of the memory cell, since a significant difference in current implies that the memory cell state has a significant voltage coefficient of resistance. An offset current applied to the mock bit line optionally may be used to provide symmetry and greater sensing margin.

Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined.

Abstract: A device may receive over a network a digitized speech signal from a remote control that accepts speech. In addition, the device may convert the digitized speech signal into text, use the text to obtain command information applicable to a set-top box, and send the command information to the set-top box to control presentation of multimedia content on a television in accordance with the command information.

Abstract: A method may include receiving, via a Session Initiation Protocol (SIP) session over a wireless fidelity (Wi-Fi) channel, a digital audio signal from a remote control configured to receive audible information; terminating, responsive to receiving the digital audio signal, the SIP session; converting the digital audio signal into text based on a number of speech grammars corresponding to program guide information; obtaining, using the program guide information, a matching set of program guide entries related to the text to determine command information corresponding to the audible information; sending, via hypertext transfer protocol or file transfer protocol, the command information to a set-top box; and generating, at the set-top box responsive to receiving the command information, a display indicative of the matching set.

Abstract: A method and apparatus for power saving for a mobile device in a wireless communication network includes a transceiver operable within an allocated spectrum of the wireless communication network. A detector is operable to detect a signal outside of the allocated spectrum of the wireless communication network transmitted from a network device. A processor is operable to configure the mobile device to be in a sleep mode wherein the transceiver is not operable and the detector is operable, and awaken the transceiver from sleep mode upon detecting the signal in order for the transceiver to communicate between an access point of the wireless communication network and the mobile device within the allocated spectrum of the wireless communication network.

Abstract: Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current comparison at a second bias state between a mock bit line and a bit line is used to determine the state of the memory cell, since a significant difference in current implies that the memory cell state has a significant voltage coefficient of resistance. An offset current applied to the mock bit line optionally may be used to provide symmetry and greater sensing margin.

Abstract: Drive signals for a display device may be generated using Separable Nonnegative Matrix Series Representation (SNMSR) of source image data and applying a non-negative matrix factorization (NNMF) process to source image data to generate approximation image data (Ii), partial sum image data (Pi) and residue image data (Ji). Iteratively, NNMF may be applied to Ji such that subsequent Ii and Ji may be generated, where each Ii can be associated with a corresponding sub-frame image. At each iteration, the Ii may be sent to the display buffer for selective activation of multiple row and column drivers during a single sub-frame interval. At each iteration, a determination may be made if a predetermined criterion is satisfied. The iterations may be terminated and the series truncated when the predetermined criterion is satisfied. Integration of the sub-frame images displayed over a complete frame interval by human eye effectively corresponds to the source image.

Abstract: A device may receive over a network a digitized speech signal from a remote control that accepts speech. In addition, the device may convert the digitized speech signal into text, use the text to obtain command information applicable to a set-top box, and send the command information to the set-top box to control presentation of multimedia content on a television in accordance with the command information.

Abstract: A random access memory architecture includes a first series connected pair of memory elements (202, 206, 302, 306, 402, 404) having a first resistance and a second series connected pair of memory elements (204, 208, 304, 308, 406, 408) having a second resistance coupled in parallel with the first series connected pair of memory elements, wherein a current flows in the first direction through both of the first and second series connected pair of memory elements. A sense amplifier (14) is coupled to an array (16) of MRAM cells (77), each including a memory element, and includes a voltage bias portion (12), the voltage bias portion including the first and second series connected pair of memory elements. The memory elements may be, for example, magnetic tunnel junctions.

Abstract: A device may receive over a network a digitized speech signal from a remote control that accepts speech. In addition, the device may convert the digitized speech signal into text, use the text to obtain command information applicable to a set-top box, and send the command information to the set-top box to control presentation of multimedia content on a television in accordance with the command information.

Abstract: A system that communicates information is described. During operation, this system receives an encryption key through a first wireless communication technique, wherein the first wireless communication technique includes near field communication. Then, the system communicates a document through a second wireless communication technique, where the document is associated with a financial transaction being conducted with a commercial establishment. Next, the system receives encrypted information through the second wireless communication technique, where the encrypted information is, at least in part, encrypted using the encryption key, and where the second wireless communication technique includes a technique other than near field communication.