Abstract: A magnetoresistive random access memory (MRAM) (900) that is susceptible to a residual magnetic field is compensated during a write operation. A first magnetic field (208) is applied to a memory cell during a first time period, the first magnetic field having a first direction (y) and a first magnitude. A second magnetic field (212) is applied to the memory cell during a second time period and having a second direction (x) and a second magnitude. A third magnetic field (702) is applied to the memory cell during a third time period, wherein the third time period overlaps at least a portion of the second time period, the third magnetic field having a third direction (?y) which is approximately opposite to the first direction of the first magnetic field. Currents are selectively applied through conductors in the memory cell to apply the three magnetic fields.

Abstract: A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

Abstract: A processor is disclosed including a register, functional unit(s), and a control unit. The register stores multiple bits, wherein one or more of the bits has a value representing a current electrical power dissipation mode (i.e., power mode) of the processor. The functional unit(s) respond to the power mode signal by altering their electrical power dissipation and issuing an acknowledge signal. The control unit receives a power mode input representing a request to enter a new power mode, and issues the power mode signal in response. The control unit waits for the acknowledge signal(s), and responds to the acknowledge signal(s) by modifying the one or more bits of the register to reflect the new power mode. A method is described for transitioning from a current power mode to a new power mode. A data processing system is disclosed including a peripheral device coupled to the processor.

Abstract: Presented herein are systems and methods for pause and freeze functions for digital video streams. A particular picture is displayed for a plurality of video display periods. A next picture is displayed at the video display period immediately following the plurality of video display periods, the next picture immediately following the particular picture in a display order. A system clock reference is loaded with a time stamp associated with the next picture when displaying the next picture.

Abstract: Presented herein are systems and methods for slow motion and high speed for digital video. In one embodiment, there is presented a method for displaying pictures. The method comprises displaying a top field from a particular picture, for a predetermined number of consecutive vertical synchronization pulses; and displaying a bottom field from the particular picture for the predetermined number of consecutive vertical synchronization pulses.

Abstract: In a magnetoresistive random access memory (MRAM), a magnetic tunnel junction (MTJ) (54) cell is stacked with an asymmetric tunnel device (56). This device, when used in a crosspoint MRAM array, improves the sensing of the state or resistance of the MTJ cells. Each MTJ cell has at least two ferromagnetic layers (42, 46) separated by an insulator (44). The asymmetric tunnel device (56) is electrically connected in series with the MTJ cell and is formed by at least two conductive layers (48, 52) separated by an insulator (50). The asymmetric tunnel device may be a MIM (56), MIMIM (80) or a MIIM (70). Asymmetry results from conducting electrons in a forward biased direction at a significantly greater rate than in a reversed biased direction. Materials chosen for the asymmetric tunnel device are selected to obtain an appropriate electron tunneling barrier shape to obtain the desired rectifying current/voltage characteristic.

Abstract: A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

Abstract: A circuit and method for counteracting stray magnetic fields generated by write currents in an MRAM memory reuses the write current in adjoining write columns via a current redistribution bus at a first end of the write lines. A first switch connected to a second end of each write line controls the write current in the write line. If the first switch is not conductive, a second switch connects the second end of the write line to a reference voltage terminal. For write lines located at sub-array edges, a predetermined amount of spacing may be used to avoid magnetic field disturbance in an adjacent sub-array. The number of spaces required can be minimized by specific activation of write line switches.

Abstract: A write driver uses a reference current that is reflected to a driver circuit by a voltage. The driver circuit is sized in relation to the device that provides the voltage so that the current through the driver is a predetermined multiple of the reference current. This voltage is coupled to the driver circuit through a switch. The switch is controlled so that the driver circuit only receives the voltage when the write line is to have write current through it as determined by a decoder responsive to an address. The driver is affirmatively disabled when the write line is intended to not have current passing through it. As an enhancement to overcome ground bounce due to high currents, the input to the driver can be capacitively coupled to the ground terminal that experiences such bounce. Additional enhancements provide benefits in amplitude and edge rate control.

Abstract: A processor is disclosed including a register, functional unit(s), and a control unit. The register stores multiple bits, wherein one or more of the bits has a value representing a current electrical power dissipation mode (i.e., power mode) of the processor. The functional unit(s) respond to the power mode signal by altering their electrical power dissipation and issuing an acknowledge signal. The control unit receives a power mode input representing a request to enter a new power mode, and issues the power mode signal in response. The control unit waits for the acknowledge signal(s), and responds to the acknowledge signal(s) by modifying the one or more bits of the register to reflect the new power mode. A method is described for transitioning from a current power mode to a new power mode. A data processing system is disclosed including a peripheral device coupled to the processor.

Abstract: A system, method, and apparatus for providing display parameters from the decode process to the display process are presented herein. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images as well as the parameters and stores each image in a separate image buffer. Additionally, the decode process stores the parameters which facilitate the display process in a buffer descriptor structure associated with the image buffer. The display process uses the parameters stored in the buffer descriptor structure during the display process.

Abstract: A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.

Abstract: A MRAM toggle type memory cell is read by first providing a first signal representative of the initial state to a sense amplifier (1300, 1500). A resistance of the cell is temporarily changed by altering a magnetic polarization of the free layer of the cell. A second signal responsive to altering the resistance of the MRAM cell is provided to the sense amplifier (1300, 1500). The first signal is compared to the second signal to determine the state of the MRAM cell.

Abstract: The state of a MRAM cell is detected when the magnetic tunnel junction (MTJ) of the MRAM cell has a reduced bias from the maximum voltage that is used for biasing. In one example, the MTJ of the selected cell and the MTJ of a reference cell are both biased to a first voltage. The MTJs then discharge this bias asymptotically (RC time constant based utilizing bit line capacitance and MTJ resistance) to a lower voltage such as ground but at rates that are different for the selected cell versus the reference cell due to MTJ resistance differential. At a predetermined time the voltage differential is detected. In another example, the MTJs are precharged to a low voltage then are driven asymptotically toward a higher voltage. Thus, at the time of sensing for both cases, the voltage across the MTJ is less than the bias voltage that is being used.

Abstract: In a magnetoresistive random access memory (MRAM), a magnetic tunnel junction (MTJ) (54) cell is stacked with an asymmetric tunnel device (56). This device, when used in a crosspoint MRAM array, improves the sensing of the state or resistance of the MTJ cells. Each MTJ cell has at least two ferromagnetic layers (42, 46) separated by an insulator (44). The asymmetric tunnel device (56) is electrically connected in series with the MTJ cell and is formed by at least two conductive layers (48, 52) separated by an insulator (50). The asymmetric tunnel device may be a MIM (56), MIMIM (80) or a MIIM (70). Asymmetry results from conducting electrons in a forward biased direction at a significantly greater rate than in a reversed biased direction. Materials chosen for the asymmetric tunnel device are selected to obtain an appropriate electron tunneling barrier shape to obtain the desired rectifying current/voltage characteristic.

Abstract: The state of a MRAM cell is detected when the magnetic tunnel junction (MTJ) of the MRAM cell has a reduced bias from the maximum voltage that is used for biasing. In one example, the MTJ of the selected cell and the MTJ of a reference cell are both biased to a first voltage. The MTJs then discharge this bias asymptotically (RC time constant based utilizing bit line capacitance and MTJ resistance) to a lower voltage such as ground but at rates that are different for the selected cell versus the reference cell due to MTJ resistance differential. At a predetermined time the voltage differential is detected. In another example, the MTJs are precharged to a low voltage then are driven asymptotically toward a higher voltage. Thus, at the time of sensing for both cases, the voltage across the MTJ is less than the bias voltage that is being used.

Abstract: A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.

Abstract: A memory provides a sensing scheme that maintains impedance balance between the route that the data takes to the sense amplifier and the route the reference or references take to the sense amplifier. Each sub-array of the memory has an adjacent column decoder that couples data to a data line that is also adjacent to the sub-array and may be considered part of the column decoder. The data for the selected sub-array is routed to the sense amplifier via its adjacent data line. The reference that is part of the selected sub-array is coupled to the data line of a non-selected sub-array. Thus the reference, which in the case of a MRAM type memory is preferably in close proximity to the location of the selected data, traverses a route to the sense amplifier that is impedance balanced with respect to the route taken by the data.

Abstract: A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.

Abstract: A magnetoresistive random access memory is operated in a toggle fashion so that its logic state is flipped from its current state to the alternate state when written. This provides for a more consistent and reliable programming because the magnetic transitional energy states during the toggle operation are stable. In a write situation, however, this does mean that the state of the cell must be read and compared to the desired state of the cell before the cell is flipped. If the cell is already in the desired logic state, then it should not be written. This read time penalty before writing is reduced by beginning the write process while reading and then aborting the write step if the cell is already in the desired state. The write can actually begin on the cell and be aborted without adversely effecting the state of the cell.